ST7LITE1XB datasheet(117/157 Pages) STMICROELECTRONICS

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ST7LITE1xB

117/157

OPERATING CONDITIONS (Cont’d)

13.3.5.2 Devices with ‘”6” or “3” order code suffix (tested for TA = -40 to +125°C) @ VDD = 3.0 to 3.6V

Notes:

1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a

decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device.

2. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 23.

3. Data based on characterization results, not tested in production

4. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy

5. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 13 on page 24.

6. This period is the PLL servoing period. During this period, the frequency remains unchanged.

7. Guaranteed by design.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fRC

Internal RC oscillator fre-

quency 1)

RCCR = FF (reset value), TA=25°C, VDD= 3.3V

700

kHz

RCCR=RCCR12) ,TA=25°C,VDD= 3.3V

992

1000

1008

ACCRC

Accuracy of Internal RC

oscillator when calibrated

with RCCR=RCCR12)

TA=25°C,VDD=3.3V

-0.8

+0.8

TA=25°C,VDD=3.0 to 3.6V

-1

TA=25 to +85°C,VDD=3.3V

-3

TA=25 to +85°C,VDD=3.0 to 3.6V

-3.5

+3.5

TA=25 to +125°C,VDD=3.0 to 3.6V

-5

+6.5

TA=-40 to +25°C,VDD=3.0 to 3.6V

-3.5

IDD(RC)

RC oscillator current con-

sumption

TA=25°C,VDD=3.3V

4003)

µA

tsu(RC)

RC oscillator setup time

TA=25°C,VDD=3.3V

102)

µs

fPLL

x4 PLL input clock

0.73)

MHz

tLOCK

PLL Lock time5)

2ms

tSTAB

PLL Stabilization time5)

4ms

ACCPLL

x4 PLL Accuracy

fRC = 1MHz@TA=25°C, VDD=2.7 to 3.3V

0.14)

fRC = 1MHz@TA=40 to +85°C, VDD= 3.3V

0.14)

tw(JIT)

PLL jitter period 6)

fRC = 1MHz

120

µs

JITPLL

PLL jitter (

∆f

CPU/fCPU)

17)

IDD(PLL)

PLL current consumption TA=25°C

1903)

µA

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