AS1181 datasheet(42/92 Pages) AMSOSRAM

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AS1181

Functional description

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DS001139 • v3-00 • 2026-Apr-01

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7.4

Serial interface description (I²C and I3C)

The device supports both I²C and I3C interface. The I3C Target is implemented according to

the MIPI-I3C Basic specification v1.1.1. The Target module is connected as a master on the

internal system bus.

The default communication mode for AS1181 is I²C, where no in-band interrupts are

generated. In the I²C mode 50ns spike filters in the pad cells are enabled.

The I²C spike filter in the pads get disabled after I3C communication is detected in the address

header (header needs to be transported with I²C timings).

In-Band-Interrupts are initially disabled and need to be enabled with the ENEC CCC.

I²C is supported up to 1Mbps (fast mode plus).

7.4.1

Operation in legacy I²C mode

I3C CCC messages are not supported in I²C systems, there are the following limitations:

•

Broadcast Strobe can be initiated by the external signal or by writing the Strobe command

code to the I2C_COMMAND_CODE register.

•

Interrupts are only asserted on output pin IRQ_N

7.4.2

I3C supported features

Table 9: I3C feature support

Feature

Supported

Single Data Rate (SDR) messaging mode up to 12.5 MHz

Yes

High Data Rate (HDR) messaging modes

Dynamic Address Assignment (DAA)

Yes

Request In-Band Interrupts

Yes

Generate Hot-Join events

Controller device capability

Legacy I²C messaging

Yes

Timing control

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