AS1181 datasheet(69/92 Pages) AMSOSRAM

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AS1181

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DS001139 • v3-00 • 2026-Apr-01

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8.3.26

TD_TRATE_MAX register (Address 0x1A34)

Table 38: TD_TRATE_MAX register (Write Access when config_mode ==1)

Addr: 0x1A34

TD_TRATE_MAX

Bit

Bit field

Default

Access

Bit description

13:0

td_trigrate_max

OTP

td_trigrate_max limit for safety check, with a resolution of

16µs (allows 1Hz resolution in the range between 5-250Hz)

Calculation:

td_trigrate_max = floor((TRATE_ideal[µs] - 17.0655) /

16.5358)

TRATE_safefail[µs] = TD_RATE_MAX * 15.49787 - 16.0863.

(all trigger delays lower than this limit will generate a FAULT)

TRATE_nofail[µs] = TD_RATE_MAX * 16.53576 + 17.0447.

(all trigger delays longer than this limit will never generate a

FAULT)

250:

4.000ms period (250Hz)

251:

4.016ms period (249Hz)

...

12093: 200ms period (5Hz)

8.3.27

TD_ILLUM_MAX register (Address 0x1A36)

Table 39: TD_ILLUM_MAX register (Write Access when config_mode ==1)

Addr: 0x1A36

TD_ILLUM_MAX

Bit

Bit field

Default

Access

Bit description

15:0

td_illum_max

OTP

td_illum_max limit for safety check, resolution: 1µs limit depends

on the values of register td_illum, td_stagger, chan_enable and

slew settings and is calculated as td_illum_max = td_illum +

(number_active_groups - 1) * td_stagger +

slew_time_last_channel

DEC 100 -> 0x0064 -> 100µs

DEC 1000 -> 0x03E8 -> 1ms

DEC 5000 -> 0x1388 -> 5ms

DEC 15000 -> 0x3A98 -> 15ms (maximum value)

>=DEC 15001 (do not use)

Note: In PWM mode ON time is constrained to be maximum

15ms. Therefore, the value in the TD_ILLUM_MAX register shall

be less the 15ms in this mode.

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