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PSD4235G2 Arkusz danych(PDF) 38 Page - STMicroelectronics |
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PSD4235G2 Arkusz danych(HTML) 38 Page - STMicroelectronics |
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38 / 89 page ![]() PSD4235G2 38/89 Figure 16. Input Macrocell External Chip Select. The CPLD also provides eight External Chip Select (ECS0-ECS7) outputs that can be used to select external devices. Each External Chip Select (ECS0-ECS7) consists of one product term that can be configured active High or Low. The output enable of the pin is controlled by either the output enable product term or the Direction Register. (See Figure 17.) Figure 17. External Chip Select Signal OUTPUT MACROCELLS A AND MACROCELLS B PT PT FEEDBACK PORT DRIVER I/O PIN INTERNAL DATA BUS DIRECTION REGISTER MUX MUX ALE/AS PT Q Q D D G LATCH INPUT MACROCELL ENABLE (.OE) D FF INPUT MACROCELL _ RD AI04926 POLARITY BIT PORT PIN ECS PT ECS To Port C or F ENABLE (.OE) PT DIRECTION REGISTER Port C or Port F AI04927 |
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