CN-0371

Circuit Note

CIRCUIT DESCRIPTION

The ADA2200 synchronous demodulator extracts position

information by filtering the LVDT secondary signal before

demodulating the signal to a low frequency output voltage that

is proportional to the LVDT core displacement. The ADA2200

drives the AD7192 24-bit Σ-Δ ADC, which digitizes and filters

the output. The ADA2200 generates the synchronous LVDT

excitation signal, and the ADG794 switch converts the CMOS

level excitation signal into a precision 3.3 V square wave to

drive LVDT primary winding.

The LVDT is an absolute displacement transducer that converts

a linear displacement into a proportional electrical signal. An

LVDT is a specially wound transformer with a moveable core

that is affixed to the position to be measured. An excitation

signal is applied to the primary windings. As the core moves,

the voltage on the secondary windings changes proportionally,

and from this voltage, position is calculated.

There are many types of LVDTs and different ways of extracting

position from them. The Figure 1 circuit uses the LVDT in 4-wire

mode. The two LVDT secondary outputs are connected such

that the voltages oppose each other, performing a subtraction.

When the LVDT core is in its null position, the voltages on each

of the two secondaries are equal, and the voltage difference

across the two windings is zero. As the core moves from the null

position, the difference voltage across the secondary windings

increases. The phase of the LVDT output voltage changes based

on direction.

The master clock for this circuit is generated by the AD7192

ADC. The ADA2200 accepts the master clock and generates

all of its internal clocks, including the reference clock used as

the LVDT excitation signal. The clock dividers on the ADA2200

are configured to provide an excitation signal of 4.8 kHz. The

ADG794 converts the excitation signal to a precision ±3.3 V

square wave from the ADC supply voltage. The 3.3 V supply is

also used as the ADC reference voltage; therefore, the ratiometric

relationship between the excitation signal and ADC reference

voltage improves the noise and stability performance of the circuit.

The 3.3 V for the system is supplied by an ADP151 low dropout

regulator driven from a 5 V supply.

The coupling circuit between the LVDT secondary windings

and the ADA2200 input is used to band limit the signal and

to adjust the relative phase between the RCLK and ADA2200

input. The circuit is configured to maximize the quadrature

(Phase = 90°) response and to minimize the in-phase (Phase = 0°)

response. This enables the position to be determined by only

measuring the quadrature output and makes the ADA2200

output voltage less sensitive to phase variations in the circuit.

The main sources of phase variation come from temperature

changes in the LVDT that cause its effective series resistance

and inductance to change.

The antialiasing filter at the ADA2200 output maintains the

signal bandwidth supported by the ADC. The output bandwidth

of the AD7192 internal digital filter is approximately 0.27 times

the output data rate. To maintain the output bandwidth at the

maximum output date rate of 4.8 kHz, the output antialiasing

filter −3 dB corner frequency is set to approximately 2 kHz. For

systems requiring lower output data rates, the antialiasing filter

corner frequency can be reduced accordingly.

Integrated Synchronous Demodulator

The ADA2200 integrated synchronous demodulator forms the

core of the circuit. It uses a unique charge sharing technology to

perform discrete time signal processing in the analog domain.

The signal path of the ADA2200 is completely differential. It

consists of a high impedance input buffer followed by a fixed

low-pass filter (FIR decimation filter), a programmable IIR

filter, a demodulator, and a differential output buffer. It has an

input and output common-mode voltage equal of 1.65 V (½ of

the 3.3 V supply voltage).

The ADA2200 accepts the 4.92 MHz clock from the AD7192

ADC and generates all of its internal clocking signals as well

as the 4.8 kHz reference clock used as the LVDT excitation

signal. The ADA2200 has configurable clock dividers that can

be programmed to support many different excitation

frequencies.

CMOS Switch

The ADG794 CMOS switch was chosen for the low on

resistance of the switches, fast switching times, break-before-

make switching action, and low cost.

The ADG794 converts the low voltage CMOS-level RCLK

output of the ADA2200 into a low impedance differential

output square wave source, which drives the LVDT. To provide

headroom for the switches to drive the positive 3.3 V signal,

the ADG794 VDD input is supplied from the 5 V power supply.

LVDT

The Figure 1 circuit supports a wide variety of LVDTs with

minor modifications. The E-100 LVDT from Measurement

Specialties, Inc., was used in 4-wire mode to demonstrate the

main attributes of the circuit. The E-100 has a stroke range of

±2.54 mm, an output sensitivity of 240 mV/V at the stroke ends,

and a maximum linearity error of ±0.5% of full-scale range.

The operating frequency range is from 100 Hz to 10 kHz. See

the E-Series LVDT data sheet for complete details.

ADA2200 Input Coupling Network

The ADA2200 input coupling network can be tuned for

different LVDTs. The inductance of the LVDT secondary

windings and the shunt capacitor (C4) form a tank circuit.

The R4 and R33 resistors reduce the Q of the tank circuit,

making the circuit less sensitive to changes in the LVDT

winding inductance and resistance at the expense of increased

power consumption. The pair of RC filters created by R34/C24

and R35/C25 reduces the signal bandwidth and provides

additional degrees of freedom for adjusting the relative phase of

the circuit. The maximum output from the ADA2200 internal

phase sensitive detector (PSD) occurs at relative phase shifts of

0° or 180°.

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