Circuit Note

CN-0371

Rev. 0 | Page 3 of 6

For the E-100 LVDT with a 4.8 kHz square wave excitation, the

optimum phase for maximum output is achieved for the following

component values:



R4 = R33 = 2.2 kΩ



R34 = R35 = 1 kΩ



C24 = C25 = 3300 pF



C4 = 0.01 μF

To tune the circuit, the phase can be measured by placing the

LVDT core to produce a near full-scale output signal. Next, make

in-phase (I) and quadrature (Q) output signal measurements.

From these measurements, the relative phase is calculated as

follows:

2

2

Q

I

A

















A

Q

REL

1

–

cos

Adjusting the network components until the absolute value of



REL

is less than approximately ±3° improves the circuit

sensitivity to variation in the LVDT electrical parameters.

ADC Selection and Synchronization

The AD7192 Σ-Δ ADC was chosen because it supports a

configurable output data rate and has different digital filter

output options, thereby allowing trade-offs between bandwidth

and noise. The master clock output feature makes it easy to lock

the frequency of the ADC sample clock to the ADA2200 output

signal. This is required to optimize the performance of the

digital filters. The desired value for determining the position

from the LVDT signal is the average value over one excitation

clock period. Therefore, when the AD7192 output date rate is

set to 4.8 kHz, exactly one excitation clock period, the desired

average is obtained. If the excitation clock period and ADC

sampling frequency are not locked, an error is induced in the

recovered position measurements. Dividing the output data rate is

effectively taking the average over multiple excitation clock periods.

The digital filter performance can be analyzed in the frequency

domain as well. Even when the LVDT core position is fixed, the

ADA2200 output signal contains energy at multiples of the

excitation signal frequency. These frequency components are

spurious error sources. The AD7192 has a sinc3 or sinc4 transfer

function with transfer function zeros at multiples of the output

data rate. The output spurs are rejected by setting the output

data rate of the ADC to the excitation signal frequency (or

submultiples of the excitation frequency). If the excitation clock

period and ADC sampling frequency are not locked, the spurs

will not fall in the nulls of the transfer function.

A complete set of documentation for the circuit including

schematics, layouts, and bill of materials can be found at

www.analog.com/CN0371-DesignSupport.

User Software for Performance Analysis

The circuit is supported with a graphical user interface that

facilitates configuring the devices on the board and evaluating

the circuit performance. Tabs are available for performing

circuit calibration and device configuration, as well as for

displaying noise performance, linearity performance, and real

time position measurements. For a complete description of the

software package, see the CN-0371 Software User Guide.

Figure 2. User Software Screen Capture

Noise Analysis

The output noise of the circuit is a function of the ADC output

data rate. Table 1 shows the effective number of bits (ENOB) in

the digitized data vs. the ADC sample rate, assuming a 2.5 V

full-scale output voltage. The noise performance of the circuit

is independent of the LVDT core position.

Table 1. Noise Performance vs. Bandwidth

ADC Data

Rate (SPS)

Output

Bandwidth (Hz)

ENOBs

(RMS)

ENOBs

(P-P)

4800

1300

14.0

11.5

1200

325

14.9

12.4

300

80

15.8

13.3

75

20

16.2

13.6

If the ADA2200 output noise were frequency independent, the

expected effective number of bits would increase by one bit for

every four-fold decrease in the output data rate. The diminishing

increase in ENOBs at the lower output data rates is caused by

the 1/f noise of the output driver that begins to dominate the

noise floor at the lower output data rates.

Linearity Test Results

The linearity results were measured by first performing a two-

point calibration at core displacements of ±2.0 mm. From these

two measurements, the slope and offset were determined to

establish an expected straight line fit. Next, measurements were

taken at core displacements across the full-scale range of

±2.5 mm. The measured data was subtracted from the expected

straight line fit data to determine the linearity error.