ST72411R datasheet(29/71 Pages) STMICROELECTRONICS

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ST72411R

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I/O PORTS (Cont’d)

5.1.3 I/O Port Implementation

The I/O port register configurations are summa-

rised as follows.

Standard Ports

PA0:7, PB5 (supplied by VDD)

PB6 (supplied by VDD)

PB0, 2, 3, 4 (supplied by VSC_PWR)

PB1 (Smartcard Data supplied by VSC_PWR)

Switching these I/O ports from one state to anoth-

er should be done in a sequence that prevents un-

wanted side effects. Recommended safe transi-

tions are illustrated in Figure 22 Other transitions

are potentially risky and should be avoided, since

they are likely to present unwanted side-effects

such as spurious interrupt generation.

Figure 22. Interrupt I/O Port State Transition

Table 7. Port Configuration

* Note: Smartcard I/Os supplied by VSC_PWR.

MODE

DDR

floating input

pull-up input with interrupt

open drain output

push-pull output

MODE

DDR

floating input

pull-down input with interrupt

open drain output

push-pull output

MODE

DDR

floating input

pull-up input with interrupt

open drain output

push-pull output

MODE

DDR

pull-up input

pull-up input with interrupt

open drain output with pull-up

push-pull output with pull-up

pull-up

interrupt

INPUT

floating

(reset state)

INPUT

open-drain

OUTPUT

push-pull

OUTPUT

= DDR, OR

Port

Pin name

Input

Output

OR = 0

OR = 1

OR = 0

OR = 1

Port A

PA7:0

floating

pull-up interrupt

open drain

push-pull

Port B

PB6

floating

pull-down interrupt

open drain

push-pull

PB5

floating

pull-up interrupt

open drain

push-pull

PB4:2 (SC*)

floating

pull-up interrupt

open drain

push-pull

PB1 (SC*)

pull-up

pull-up interrupt

pull-up open drain

pull-up push-pull

PB0 (SC*)

floating

pull-up interrupt

open drain

push-pull

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