ST72411R datasheet(48/71 Pages) STMICROELECTRONICS

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ST72411R

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SMARTCARD SUPPLY SUPERVISOR (Cont’d)

5.5.5 Register Description

CONTROL/STATUS REGISTER (SSSCR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = Reserved, forced by hardware to 0.

Bit 6 = CKOD

Clock output division

This bit is set and cleared by software. It selects

the frequency division factor of the SC_CK output

clock.

0: SC_CK clock output frequency = fosc /2.

1: SC_CK clock output frequency = fosc /4.

Bit 5 = CK_AFOEN

Clock AF output enable

This bit is set and cleared by software.

0: The SC_CK alternate function is disabled. The

I/O port is free for general purpose I/O.

1: The SC_CK alternate function is enabled. The

clock is output on the I/O port.

Bit 4 = OVLDF

Overload flag

This bit is set by hardware when the SC_PWR out-

put voltage drops due to current overload. It is set

when a falling edge is detected on SC_PWR and

when SC_PWR is under the Overload Voltage

Level. This bit can only be cleared by software.

0: No Current Overload

1: Current Overload

Bit 3 = OVLDIE

Overload interrupt enable

This bit is set and cleared by software.

0: OVLD interrupt disabled.

1: OVLD interrupt enabled.

Bit 2= OVLDEN

Current overload detector enable

This bit is set and cleared by software. This bit

must be set only when SSSEN =1.

0: Current Overload Detection disabled.

1: Current Overload Detection enabled.

Bit 1 = SSSR

Smartcard supply regulation

This bit is set and cleared by software. Refer to

Figure 52 for recommended transitions.

0: The regulation voltage output is 3V.

1: The regulation voltage output is 5V.

Bit 0 = SSSEN

SSS module enable

This bit can only be set by software. It can be

cleared by software. It is cleared by hardware

when OVLDF=1 (current overload condition).

0: SSS is disabled.

1: SSS is enabled.

7654

321

CKOD

CK_A

FOEN

OV-

LDF

OV-

LDIE

OV-

LDEN

SSSR

SS-

SEN

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