AD7152 datasheet(12/24 Pages) AD

12 / 24 page

AD7152/AD7153

Rev. 0 | Page 12 of 24

The user can also access any unique register (address) on a

one-to-one basis without having to update all the registers.

However, the address pointer register contents cannot be read.

If an incorrect address pointer location is accessed, or if the user

allows the autoincrementer to exceed the required register

address, apply the following requirements:

•

In read mode, the AD7152/AD7153 continue to output

various internal register contents until the master device

issues a no acknowledge, start, or stop condition. The

contents of the address pointers autoincrementer are reset

to point to the status register at Address 0x00 when a stop

condition is received at the end of a read operation. This

allows the status register to be read (polled) continually

without having to constantly write to the address pointer.

•

In write mode, the data for the invalid address is not

loaded into the registers of the AD7152/AD7153, but

an acknowledge is issued by the AD7152/AD7153.

AD7152/AD7153 RESET

To reset the AD7152/AD7153 without having to reset the entire

I2C bus, an explicit reset command is provided. This command

uses a particular address pointer word as a command word to

reset the part and upload all default settings. The AD7152/

AD7153 do not respond to the I2C bus commands (no acknowl-

edge) during the default values upload for approximately 150 μs

(maximum 200 μs).

The reset command address word is 0xBF.

GENERAL CALL

When a master issues a slave address consisting of seven 0s with

the eighth bit (R/W bit) set to 0, this is called the general call

address. The general call address is for addressing every device

connected to the I2C bus. The AD7152/AD7153 acknowledge

this address and read the following data byte.

If the second byte is 0x06, the AD7152/AD7153 are reset,

completely uploading all default values. The AD7152/AD7153

do not respond to the I2C bus commands (no acknowledge)

during the default values upload for approximately 150 μs

(maximum 200 μs).

The AD7152/AD7153 do not acknowledge any other general

call commands.

1 to 7

START

ADDR

R/W

ACK

SUBADDRESS

ACK

DATA

ACK

STOP

SDA

SCL

Figure 22. Bus Data Transfer

DATA

A(S)

S SLAVE ADDR A(S)

SUB ADDR

A(S)

LSB = 0

LSB = 1

DATA

S SLAVE ADDR A(S)

SUB ADDR A(S) S SLAVE ADDR

A(S)

DATA

A(M)

DATA

WRITE

SEQUENCE

READ

SEQUENCE

A(S)

A(M)

Figure 23. Write and Read Sequences

Table 5. I2C Abbreviation

Abbreviation

Definition

Start bit

Stop bit

A(S)

Acknowledge by slave

A(M)

Acknowledge by master

A(S)

No acknowledge by slave

A(M)

No acknowledge by master

ACK

Acknowledge

R/W

Read/write

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