STE100 datasheet(30/66 Pages) STMICROELECTRONICS

30 / 66 page

STE10/100

30/66

7~0

PAB0

physical address byte 0

From

EEPROM

R/W

CSR26(offset = a8h) - PAR1, physical address register 1, automatically recalled from EEPROM

31~24

---

reserved

23~16

---

reserved

15~8

PAB5

physical address byte 5

From

EEPROM

R/W

7~0

PAB4

physical address byte 4

From

EEPROM

R/W

For example, physical address = 00-00-e8-11-22-33

PAR0= 11 e8 00 00

PAR1= XX XX 33 22

PAR0 and PAR1 are readable, but can be written only if the receive state is in stopped (CSR5 bits 19-17=000).

CSR27(offset = ach) - MAR0, multicast address register 0

31~24

MAB3

multicast address byte 3 (hash table 31:24)

00h

R/W

23~16

MAB2

multicast address byte 2 (hash table 23:16)

00h

R/W

15~8

MAB1

multicast address byte 1 (hash table 15:8)

00h

R/W

7~0

MAB0

multicast address byte 0 (hash table 7:0)

00h

R/W

CSR28(offset = b0h) - MAR1, multicast address register 1

31~24

MAB7

multicast address byte 7 (hash table 63:56)

00h

R/W

23~16

MAB6

multicast address byte 6 (hash table 55:48)

00h

R/W

15~8

MAB5

multicast address byte 5 (hash table 47:40)

00h

R/W

7~0

MAB4

multicast address byte 4 (hash table 39:32)

00h

R/W

MAR0 and MAR1 are readable, but can be written only if the receive state is in stopped(CSR5 bit19-17=000).

Table 6. Control/Status register description

Bit #

Name

Descriptions

Default Val

RW Type

STE100 Arkusz danych(PDF) 30 Page - STMicroelectronics

STE100 Arkusz danych(HTML) 30 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

Arkusz danych Pobierz

Link URL