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STE100 Arkusz danych(PDF) 42 Page - STMicroelectronics

Numer części STE100
Szczegółowy opis  PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V
PDF  66 Pages
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Producent  STMICROELECTRONICS [STMicroelectronics]
Strona internetowa  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STE100 Arkusz danych(HTML) 42 Page - STMicroelectronics

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6.2 Network Packet Buffer Management
6.2.1 Descriptor Structure Types
During normal network transmit operations, the STE10/100 transfers the data packets from transmit buffers in
the host’s memory to the STE10/100’s transmit FIFO. For receive operations, the STE10/100 transfers the data
packet from its receive FIFO to receive buffers in the host’s memory. The STE10/100 makes use of descriptors,
data structures which are built in host memory and contain pointers to the transmit and receive buffers and main-
tain packet and frame parameters, status, and other information vital to controlling network operation.
There are two types of structures employed to group descriptors, the Ring and the Chain, both supported by
the STE10/100 and shown below. The selection of structure type is controlled by RCH (RDES1 bit 24) and TCH
(TDES1 bit 24).
The transmit and receive buffers reside in the host’s memory. Any buffer can contain either a complete or partial
packet. A buffer may not contain more than one packet.
s
Ring structure: There are two buffers per descriptor in the ring structure. Support receive early interrupt.
Figure 5. Ring structure of frame buffer
own
Data Buffer
Length 1
Data
Data
Length 2
Buffer1 pointer
Buffer2 pointer
Length 2 Length 1
Descriptor
.
.
.
.
.
.
.
Descriptor Pointer
CSR3 or CSR4
End of Ring



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