STULPI01A datasheet(32/44 Pages) STMICROELECTRONICS

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ULPI registers

STULPI01A - STULPI01B

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Table 17.

Function control register

04h-06h(Read), 04h(Write), 05h(Set), 06h(Clear)

(Controls UTMI function setting of the USB transceiver PHY)

Field name

Bits

Access

Reset

Description

XcvrSelect

1:0

rd/wr/s/c

01b

Selects the required transceiver speed.

00b: Enable HS transceiver

01b: Enable FS transceiver

10b: Enable LS transceiver

11b: Enable FS transceiver for LS packets (FS preamble

is automatically pre-pended)

IMPORTANT NOTE: Every time the XcvrSelect is

changed to ‘00’, the output ULPI clock is stopped for the

time needed for internal DLL calibration.

TermSelect

rd/wr/s/c

Controls the internal pull-up resistors or HS terminations.

Control over these resistors changes depending on

XcvrSelect, OpMode, DpPulldown and DmPulldown, as

shown in Table 24.

OpMode

4:3

rd/wr/s/c

00b

Selects the required bit encoding style during transmit.

00b: Normal operation

01b: Non-driving

10b: Disables bit-stuff and NRZI encoding

11b: Do not automatically add SYNC and EOP when

transmitting. Must be used only for HS packets.

Reset

rd/wr/s/c

Active high transceiver reset. After the Link sets this bit,

STULPI01 asserts DIR and reset the UTMI+ core. When

the reset is completed, STULPI01 de-asserts DIR and

automatically clears this bit. After de-asserting DIR,

STULPI01 re-asserts DIR and sends an RX CMD update

to the Link.

Note: If Reset bit is set to ‘1’ and SuspendM bit is set to ‘0’

in the same register access, SuspendM bit takes higher

priority and chip will enter low power mode. Reset bit will

be cleared.

SuspendM

rd/wr/s/c

Active low PHY suspend. Puts PHY into Low Power

Mode. STULPI01 automatically sets this bit to ‘1’ when

Low Power Mode is exited.

0b: Low Power Mode

1b: Powered

Note: If Reset bit is set to ‘1’ and SuspendM bit is set to ‘0’

in the same register access, SuspendM bit takes higher

priority and chip will enter low power mode. Reset bit will

be cleared.

Reserved

rd/wr/s/c

Reserved

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