STA011 datasheet(18/38 Pages) STMICROELECTRONICS

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I2C-bus interface

STA011

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5.1.7

Transmission without acknowledge

To avoid detecting an acknowledge from the STA011, the µP can use a simpler

transmission: simply it waits one clock period without checking the STA011 acknowledging,

and sends the new data. This approach of course is less protected from data corruption.

5.1.8

Device addressing

To start the communication between the master and the STA011, the master must initiate

with a start condition. Following this, the master sends onto the SDA line 8 bits (MSB first)

corre-sponding to the device select address and read or write mode.

The first 7 MSB`s are the device address identifier, corresponding to the I2C-bus definition.

For the STA011 these are fixed as 110000A. The A bit is reset to 0 internally by a pull-down

re-sistor but it can be changed through the corresponding external pin Address. In this way if

the Address pin is floating the address is fixed to the previous configuration (110000),

otherwise if the pin is set high the address is fixed to 1100001.

The 8th bit (LSB) is the read or write operation bit (RW; set to 1 in read mode and to 0 in

write mode). After a START condition the STA011 identifies on the Bus the device address

and, if matched, it will acknowledge the identification on the SDA bus during the 9th clock

pulse.

The following byte after the device identification byte, is the internal sub-address byte that

provides access to any of the internal registers.

5.1.9

Write operation (single byte write)

Following a START (S) condition the master sends a device select code with the RW bit set

to 0. The I2C gives the acknowledgement and waits for the 1 byte of internal sub address.

This byte provides access to any of the internal registers.

After the reception of the internal byte sub address the I2C again responds with an acknowl-

edgement. The master terminates the transfer by generating a STOP (P) condition.

A single byte write with sub-address 00H would affect DATA_OUT[119:112], so a single byte

write with sub-address 02H would affect DATA_OUT[103:96] and so on

A single byte address with sub-address out of ranges 00H - 0FH produces

illegal_subaddress signal to go high and DATA_OUT[119:0] will not change until a

successive write operation request with the correct range for sub-address will be made.

For example if the sub-address is 15H will be produced illegal_subaddress = '1' and

DATA_OUT will no change.

5.1.10

Write operation (multibyte write)

The multi-byte write mode can start from any internal sub address (the same as a single

byte write).

Following a START (S) condition the master sends a device select code with the RW bit set

to 0. The I2C gives the acknowledgement and waits for 1 byte from the internal sub address.

This byte provides the starting byte of the internal registers.

110000A

R/W 0

ack

Sub-address byte

ack

DATA IN

ack

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