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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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M16C/29 Arkusz danych(PDF) 99 Page - Renesas Technology Corp |
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M16C/29 Arkusz danych(HTML) 99 Page - Renesas Technology Corp |
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99 / 499 page  9. Interrupts p u o r G 9 2 / C 6 1 M page 75 8 5 4 f o 7 0 0 2 , 0 3 .r a M 2 1 . 1 . v e R 2 1 1 0 - 1 0 1 0 B 9 0 J E R 9.3 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to nonmaskable interrupts. Use I flag in the the FLG register, IPL, and bits ILVL2 to ILVL0 in the each interrupt control register to enable/disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control register. Figure 9.3 shows the interrupt control registers. Also, the following interrupts share a vector and an interrupt control register. ________ •INT4 and SIO3 ________ •INT5 and SIO4 •A/D converter and key input interrupt •IC/OC base timer and SCL/SDA •IC/OC interrupt 1 and I2C bus interface An interrupt request is set by bits IFSR6 and IFSR7 in the IFSR register and bits IFSR27, IFSR26, and IFSR21 in the IFSR2A register. Figure 9.4 shows registers IFSR register and IFSR2A. |
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