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7733 Arkusz danych(PDF) 482 Page - Renesas Technology Corp |
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7733 Arkusz danych(HTML) 482 Page - Renesas Technology Corp |
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482 / 940 page  LOW VOLTAGE VERSION 7733 Group User’s Manual 18–16 18.4 Electrical characteristics 18.4.6 Ready and Hold Timing requirements (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz (Note), unless otherwise noted) g The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Limits tsu(RDY–φ1) tsu(HOLD–φ1) th(φ1–RDY) th(φ1–HOLD) Max. ns ns ns ns Min. Parameter Symbol Unit 80 80 0 0 Note: This is applied to the case where the main clock division selection bit = “0” and f(f2) = 6 MHz. Switching characteristics (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz, unless otherwise noted) ns Min. Max. 120 Limits Unit Conditions Parameter Fig. 18.4.1 Symbol _____ HLDA output delay time td(φ1–HLDA) ____ RDY input setup time _____ HOLD input setup time ____ RDY input hold time _____ HOLD input hold time |
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