7733 datasheet(102/940 Pages) RENESAS

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7733 Group User's Manual

4–23

INTERRUPTS

; The write instruction for the interrupt priority level selection bits

; The NOP instruction is inserted (Note)

;

; The write instruction for the interrupt priority level selection bits

Note: Other instructions whose cycle number corresponds to that of the NOP instruction

(other than the write instructions for address 7X 16) can be inserted.

For number of the NOP instructions which are to be inserted, refer to Table 4.11.1.

LDM .B #0XH, 007XH

NOP

LDM .B #0XH, 007XH

4.11 Precautions for interrupts

When the contents of the interrupt priority level selection bits (bits 0 to 2 at addresses 7016 to 7F16) is

changed, 2 to 7 cycles of

φ are required. Therefore, when the interrupt priority level of the same interrupt

source is changed twice or more in a very short time, which consists of a few instructions, it is necessary

to secure the required time by software. Figure 4.11.1 shows an program example to secure the time

required for the change of an interrupt priority level. Note that the time required for the change depends on

the contents of the interrupt priority level selection bits (bits 4 and 5 at address 5E16). Table 4.11.1 lists the

correspondence between the number of instructions inserted in a program example and the interrupt priority

level selection bits. (Refer to Figure 4.11.1, also.)

4.11 Precautions for interrupts

Table 4.11.1 Correspondence between number of instructions to be inserted in Figure 4.11.1 and

interrupt priority detection time selection bits

Interrupt priority detection time selection bits (Note)

Time required for change of

interrupt priority level

Number of inserted

NOP instruction

7 cycles of

4 cycles of

2 cycles of

4 or more

2 or more

1 or more

Set as follows, if possible:

[b5 = “1,” b4 = “0”]

Fig. 4.11.1 Program example to secure time required for change of interrupt priority level

Do not select.

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