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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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TDA9109 Arkusz danych(PDF) 6 Page - STMicroelectronics |
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TDA9109 Arkusz danych(HTML) 6 Page - STMicroelectronics |
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6 / 30 page  ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VCC Supply Voltage (Pin 29) 13.5 V VDD Supply Voltage (Pin 32) 5.7 V VIN Max Voltage on Pin 4 Pin 5 Pins 6, 7, 8, 14, 15, 16, 20, 22 Pins 9, 10, 18, 23, 24, 25, 26, 28 Pins 1, 2, 3, 30, 31 4.0 6.4 8.0 VCC VDD V V V V V VESD ESD susceptibility Human Body Model,100pF Discharge through 1.5k Ω EIAJ Norm, 200pF Discharge through 0 Ω 2 300 kV V Tstg Storage Temperature -40, +150 oC Tj Junction Temperature +150 oC Toper Operating Temperature 0, +70 oC THERMAL DATA Symbol Parameter Value Unit Rth (j-a) Junction-Ambient Thermal Resistance Max. 65 oC/W SYNC PROCESSOR Operating Conditions (VDD =5V, Tamb =25 oC) Symbol Parameter Test Conditions Min. Typ. Max. Unit HsVR Voltage on H/HVIN Input Pin 1 0 5 V MinD Minimum Horizontal Input Pulses Duration Pin 1 0.7 µs Mduty Maximum Horizontal Input Signal Duty Cycle Pin 1 25 % VsVR Voltage on VSYNCIN Pin 2 0 5 V VSW Minimum Vertical Sync Pulse Width Pin 2 5 µs VSmD Maximum Vertical Sync Input Duty Cycle Pin 2 15 % VextM Maximum Vertical Sync Width on TTL H/Vcomposite Pin 1 750 µs IHLOCKOUT Sink and Source Current Pin3 250 µA Electrical Characteristics (VDD =5V, Tamb =25 oC) Symbol Parameter Test Conditions Min. Typ. Max. Unit VINTH Horizontal and Vertical Input Logic Level (Pins 1, 2) Low Level High Level 2.2 0.8 V V RIN Horizontal and Vertical Pull-Up Resistor Pins 1, 2 200 k Ω TfrOut Fall and Rise Time, Output CMOS Buffer Pin 3, COUT = 20pF 200 ns VHlock Horizontal 1st PLL Lock Output Status (Pin 3) Locked, ILOCKOUT = -250 µA Unlocked, ILOCKOUT = +250 µA 4.4 0 5 0.5 V V VoutT Extracted Vsync Integration Time (% of TH) on H/V Composite (see Note 1) C0 = 820pF 26 35 % Note 1 : TH is the horizontal period. I 2C READ/WRITE (see Note 2) Electrical Characteristics (VDD =5V,Tamb =25 oC) Symbol Parameter Test Conditions Min. Typ. Max. Unit I 2C PROCESSOR Fscl Maximum Clock Frequency Pin 30 400 kHz Tlow Low period of the SCL Clock Pin 30 1.3 µs Thigh High period of the SCL Clock Pin 30 0.6 µs Vinth SDA and SCL Input Threshold Pins 30,31 2.2 V VACK Acknowledge Output Voltage on SDA input with 3mA Pin 31 0.4 V Note 2 : See also I 2C Table Control and I2C Sub Address Control. TDA9109/SN 6/30 |
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