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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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AD8366 Arkusz danych(PDF) 4 Page - Analog Devices |
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AD8366 Arkusz danych(HTML) 4 Page - Analog Devices |
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4 / 13 page  AD8366 Preliminary Technical Data Rev. PrC | Page 4 of 13 OIP3 2 V p-p composite, Max. Gain, ZL=500Ώ 34.2 dBVrms 2 V p-p composite, Min. Gain, ZL=500Ώ 30.7 dBVrms Output 1 dB Compression Point Max. gain, ZL=500Ώ 6.7 dBVrms Min. Gain, ZL=500Ώ 7.2 dBVrms 100 MHz Noise Figure Max Gain 11.84 dB Min Gain 18.8 dB 2nd Harmonic 2 Vp-p output , Max Gain TBD dBc Min Gain TBD dBc 3rd Harmonic 2 Vp-p output, Max Gain TBD dBc Min Gain TBD dBc OIP3 2Vp-p composite, Max. Gain @ 500 Load impedance 29.5 dBVrms Min. Gain 21 dBVrms Output 1 dB Compression Point Max. gain 4 dBVrms Min. Gain 6 dBVrms DIGITAL LOGIC SENB, DENA, DENB, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5 VINH, Input High Voltage TBD V VINL, Input Low Voltage TBD V IINH/IINL, Input Current TBD μA CIN, Input Capacitance TBD pF SPI INTERFACE TIMING SENB = HIGH fSCLK TBD MHz t1 CS rising edge to first SCLK rising edge TBD ns t2 SCLK high pulse width TBD ns t3 SCLK low pulse width TBD ns t4 SDAT setup time TBD ns t5 SDAT hold time TBD ns t6 SCLK falling edge to CS low TBD ns PARALLEL PORT TIMING SENB = LOW t7 DENA/B high pulse width TBD ns t8 DENA/B low pulse width TBD ns t9 BIT[0-5] setup time TBD ns t10 BIT[0-5] hold time TBD ns POWER AND ENABLE VPSI, VPSO, ICOM, OCOM, ENBL Supply Voltage Range 4.5 5.5 V Total Supply Current ENBL = 5V 180 mA Disable Current ENBL = 0V 3.2 mA Disable Threshold TBD V Enable Response Time Delay following high-to-low transition until device meets full specifications TBD ns Disable Response Time Delay following low-to-high transition until device produces full attenuation TBD ns |
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