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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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ADATE305 Arkusz danych(PDF) 34 Page - Analog Devices |
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ADATE305 Arkusz danych(HTML) 34 Page - Analog Devices |
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34 / 56 page  ADATE305 Rev. 0 | Page 34 of 56 SPI DETAILS SCLK CS SDIN tCH tCL tCSSA tCSHA tCSHD tCSSD tDH tDS tCSW SDOUT DO_2LAST DO_12LAST DO_13LAST DO_14LAST DO_15LAST DO_1LAST DO_0LAST tDO DATA[14] DATA[15] CH[1] R/W ADDR[1] ADDR[0] Figure 67. SPI Timing Diagram Table 17. Serial Peripheral Interface Timing Requirements Symbol Parameter Min Max Unit tCH SCLK minimum high 9.0 ns tCL SCLK minimum low 9.0 ns tCSHA CS assert hold 3.0 ns tCSSA CS assert setup 3.0 ns tCSHD CS deassert hold 3.0 ns tCSSD CS deassert setup 3.0 ns tDH SDIN hold 3.0 ns tDS SDIN setup 3.0 ns tDO SDOUT Data Out 15.0 ns tCSW CS minimum between assertions1 2 SCLK cycles CS minimum directly after a read request 3 SCLK cycles tCSTP Minimum delay after CS is deasserted before SCLK can be stopped (not shown in ); this allows any internal operations to complete Figure 67 16 SCLK cycles 1 An extra cycle is needed after a read request to prime the read data into the SPI shift register. |
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