ADATE305 datasheet(46/56 Pages) AD

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ADATE305

Rev. 0 | Page 46 of 56

RECOMMENDED PMU MODE SWITCHING

SEQUENCES

To minimize any possible aberrations and voltage spikes on the

DUT output, specific mode switching sequences are

recommended for the following transitions:

•

PMU disable to PMU enable.

•

PMU force voltage mode to PMU force current mode.

•

PMU force current mode to PMU force voltage mode.

PMU Disable to PMU Enable

Note that in Table 39 through Table 49, X indicates the don’t care bit.

Step 1. Table 39 lists the state of the registers in PMU disabled mode.

Table 39.

Bits

Setting

PE/PMU Enable Register, ADDR[4:0] = 0x0C

DATA[2]

PMU State Register, ADDR[4:0] = 0x0E

DATA[9:8]

DATA[7]

DATA[6]

DATA[5]

DATA[4]

DATA[3]

DATA[2:0]

XXX

Step 2. Write to Register ADDR[4:0] = 0x0E (see Table 40).

Table 40.

Bits

Setting

Comments

PMU State Register, ADDR[4:0] = 0x0E

DATA[9:8]

1X or 00

Set desired input selection

DATA[7]

DATA[6]

DATA[5]

DATA[4]

DATA[3]

This bit must be set to force voltage mode to reduce

aberrations

DATA[2:0]

XXX

Set desired range

Step 3. Write to Register ADDR[4:0] = 0x0C (see Table 41).

Table 41.

Bits

Setting

Comments

PE/PMU Enable Register, ADDR[4:0] = 0x0C

DATA[2]

PMU is now enabled in force voltage mode

PMU Force Voltage Mode to PMU Force Current Mode

Step 1. Table 42 lists the state of registers in force voltage mode.

Table 42.

Bits

Setting

PE/PMU Enable Register, ADDR[4:0] = 0x0C

DATA[2]

PMU State Register, ADDR[4:0] = 0x0E

DATA[9:8]

DATA[7]

DATA[6]

DATA[5]

DATA[4]

DATA[3]

DATA[2:0]

XXX

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