MPC8640D datasheet(18/140 Pages) FREESCALE

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MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

DDR and DDR2 SDRAM

Table 11 provides the PLL lock times.

DDR and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the

MPC8640. Note that DDR SDRAM is Dn_GVDD(typ) = 2.5 V and DDR2 SDRAM is

Dn_GVDD(typ) = 1.8 V.

6.1

DDR SDRAM DC Electrical Characteristics

Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the

MPC8640 when Dn_GVDD(typ) = 1.8 V.

Table 10. RESET Initialization Timing Specifications

Parameter/Condition

Min

Max

Unit

Notes

Required assertion time of HRESET

100

—

μs

Minimum assertion time for SRESET_0 & SRESET_1

—

SYSCLKs

Platform PLL input setup time with stable SYSCLK

before HRESET negation

100

—

μs2

Input setup time for POR configs (other than PLL

config) with respect to negation of HRESET

—

SYSCLKs

Input hold time for all POR configs (including PLL

config) with respect to negation of HRESET

—

SYSCLKs

Maximum valid-to-high impedance time for actively

driven POR configs with respect to negation of

HRESET

—

SYSCLKs

Notes:

1. SYSCLK is the primary clock input for the MPC8640.

2 This is related to HRESET assertion time. Stable PLL configuration inputs are required when a stable SYSCLK is

applied. See the

MPC8641D Integrated Host Processor Reference Manual for more details on the power-on reset

sequence.

Table 11. PLL Lock Times

Parameter/Condition

Min

Max

Unit

Notes

(Platform and E600) PLL lock times

—

100

μs1

Local bus PLL

—

μs

Notes:

1. The PLL lock time for e600 PLLs require an additional 255 MPX_CLK cycles.

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