CS47048 datasheet(22/34 Pages) CIRRUS

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CS47048 Data Sheet

Audio SOC Processor Family

DS787A7

5.14 Digital Switching Characteristics — Digital Audio Output Port

Figure 9. Digital Audio Output Port Timing, Master Mode

Parameter

Symbol

Min

Max

Unit

DAO_MCLK period

Tdaomclk

DAO_MCLK duty cycle

DAO_SCLK period for Master or Slave mode1

1. Master mode timing specifications are characterized, not production tested.

Tdaosclk

DAO_SCLK duty cycle for Master or Slave mode1

-40

Master Mode (Output A1 Mode)1,2

2. Master mode is defined as the CS47048 driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it

is divided to produce DAO_SCLK, DAO_LRCLK.

DAO_SCLK delay from DAO_MCLK rising edge,

DAO_MCLK as an input

tdaomsck

-19

DAO_LRCLK to DAO_SCLK non-active edge3, See Figure 9A.

3. The DAO_LRCLK transition may occur on either side of the non-active edge of DAO_LRCLK. The active edge

of DAO_SCLK is the point at which the data is valid.

tdaomlrts

-8

DAO_SCLK non-active edge3 to DAO_LRCLK, See Figure 9B

tdaomstlr

-8

DAO_DATA[3..0] delay from DAO_SCLK non-active edge3

tdaomdv

-8

Slave Mode (Output A0 Mode)4

4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.

DAO_LRCLK to DAO_SCLK non-active edge3, See Figure 10A.

tdaoslrts

-15

DAO_SCLK non-active edge3 to DAO_LRCLK, See Figure 10B.

tdaosstlr

-30

DAO1_DATA[3..0] delay from DAO_SCLK non-active edge3

tdaosdv

-8

DAO_MCLK

DAO_SCLK

DAO_LRCLK

DAO_DATAn

tdaomsck

tdaomlrts

tdaomdv

tdaomclk

DAO_MCLK

DAO_SCLK

DAO_LRCLK

DAO_DATAn

tdaomclk

tdaomstlr

tdaomdv

tdaomsck

A. DAO_LRCLK transition before DAO_SCLK non-active

edge. See Footnote 3 on page 22.

B. DAO_LRCLK transition after DAO_SCLK non-active

edge. See Footnote 3 on page 22.

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