LTC6907

5

6907fa

4

6

1

OP AMP

150

Ω DRIVER

OUT

6907 BD

3

DIV

PROGRAMMABLE

DIVIDER (n)

(

÷1, ÷3, ÷10)

THREE-LEVEL

INPUT

DETECTOR

VOLTAGE

CONTROLLED

OSCILLATOR

(MASTER OSCILLATOR)

SET

2

GND

FREQUENCY-TO-CURRENT

CONVERTERS

BUFFER

GRD

5M

5M

DIVIDER

SELECT

5

50k

Ω

PI FU CTIO S

OUT (Pin 1): Oscillator Output. The OUT pin swings from

150

Ω. For micropower operation, the load resistance

must be kept as high as possible and the load capacitance

as low as possible.

GND (Pin 2): Ground.

DIV (Pin 3): Divider Setting Input. This three-level input

selects one of three internal digital divider settings, deter-

mining the value of N in the frequency equation. Tie to GND

for

floating, the LTC6907 pulls Pin 3 to mid-supply with a

2.5M resistor. When Pin 3 is floating, care should be taken

to reduce coupling from the OUT pin and its trace to Pin 3.

Coupling can be reduced by increasing the physical space

between traces or by shielding the DIV pin with grounded

metal.

SET (Pin 4): Frequency Setting Resistor Input. Connect a

frequency. For best performance use a precision metal or

thin-film resistor of 0.1% or better tolerance and 50ppm/

°C

or better temperature coefficient. For lower accuracy

applications, an inexpensive 1% thick-film resistor may be

than 10pF to reduce jitter and to ensure stability. The

voltage on the SET pin is approximately 650mV at 25

°C

and decreases with temperature by about –2.3mV/

°C.

GRD (Pin 5): Guard Signal. This pin can be used to reduce

PC board leakage across the frequency setting resistor,

pin and shunts leakage current away from the SET pin. To

control leakage, connect a bare copper trace (a trace with

no solder mask) to GRD and loop it around the SET pin and

all PC board metal connected to SET. Careful attention to

board layout and assembly can prevent leakage currents.

The use of a guard ring provides additional shielding of

leakage currents from the SET pin and is optional. If

unused, the GRD pin should be left unconnected.

µF

decoupling capacitor should be placed as close as pos-

sible to this pin for best performance.

BLOCK DIAGRA