GC4014 datasheet(21/46 Pages) TI

21 / 46 page

GRAYCHIP, INC.

- 16 -

APRIL 27, 1999

GC4014 QUAD RECEIVER CHIP

DATA SHEET REV 0.6

This document contains information which may be changed at any time without notice

5.0

CONTROL REGISTERS

The chip is configured and controlled through the use of eight bit control registers. These registers are

accessed for reading or writing using the control bus pins (CE, RD, WR, A[0:4], and C[0:7]) described in the

previous section. The register names and their addresses are:

The Mode and Control Registers are addresses 0 to 15

ADDRESS

NAME

ADDRESS

NAME

Sync Mode

Blank Control

Decimation Mode

Channel Flush Control

Decimation Byte 0

Counter Byte 0

Decimation Byte 1

Counter Byte 1

Scale Control

Test Mode

Channel Gain

Page Map

Output Format

Status

Output Mode

Checksum

Addresses 16 to 31 are used in sixteen pages as determined by the page select control bits in the page map

PAGE

NAME

PAGE

NAME

Channel Outputs

Coefficients 0 to 7

Keepalive Status

Coefficients 8 to 15

unused

Coefficients 16 to 23

unused

Coefficients 24 to 31

Channel Control A

unused

Channel Control B

unused

Channel Control C

unused

Channel Control D

unused

The following sections describe each of these registers. The type of each register bit is either R, W, or R/W

indicating whether the bit is read only, write only, or read/write. All bits are active high.

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