GC4014 datasheet(22/46 Pages) TI

22 / 46 page

GRAYCHIP, INC.

- 17 -

APRIL 27, 1999

GC4014 QUAD RECEIVER CHIP

DATA SHEET REV 0.6

This document contains information which may be changed at any time without notice

5.1

SYNC MODE REGISTER

The Sync mode control register determines how the circuits within the chip are synchronized. Each circuit

which requires synchronization can be configured to be synchronized to the sync input (SI), or to the terminal count

of the sync counter (TC). The sync to each circuit can also be set to be always on or always off. Each circuit is given

a two bit sync mode control which is defined as:

NOTE: the internal syncs are active high. The SI input has been inverted to be the active high sync SI.

ADDRESS 0:

Sync Mode

, suggested default = 0x65

BIT

TYPE

NAME

DESCRIPTION

0,1 (LSBs)

R/W

DEC_SYNC

Synchronizes the decimation control counter. The decimation counter

controls the filter timing of each channel and the serial timing of the

output signals.

2,3

R/W

COUNTER_SYNC

Synchronizes the sync counter. This counter is used to generate the

periodic “TC” sync pulses. Mode 2 in Table 4 is always OS.

4,5

R/W

OUTPUT_SYNC

The selected sync is inverted and output on the SO pin.

R/W

USE_ONESHOT

The terminal count mode in table 4 is replaced by the one shot pulse

(OS) when this bit is set.

R/W

ONE_SHOT

The one shot sync pulse (OS) is generated when this bit is set. This

bit must be cleared before another one shot pulse can be generated.

If the user wishes to allow the chip to free run, asynchronous to other chips, then the sync settings can be

set to zero. If one wishes to synchronize several chips to a single sync source, then the sync mode selections should

be set to one. The suggested default is to output the one-shot (USE_ONESHOT = 1, OUTPUT_SYNC=2) and set

all other syncs to SI. The user should tie the SO output pin of one GC4014 chip to the SI input pin of all other GC4014

chips in a system in order to cleanly synchronize and initialize one or more GC4014 chips. If there is only a single

GC4014 chip, then all sync mode selections can be set to “2” to receive the one-shot directly. A one-shot should be

sent after initialization and each time the decimation ratio is changed.

Table 4: Sync Modes

MODE

SYNC DESCRIPTION

“0” (never asserted)

1SI

TC (or OS, if USE_ONESHOT is set)

“1” (always active)

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