September 2006

PCS2P20805A

rev 0.3

2.5V CMOS Dual 1-To-5 Clock Driver

5 of 11

Notice: The information in this document is subject to change without notice.

Switching Characteristics Over Operating Range

3,4

Symbol

Parameter

Conditions

1

Min

2

Max

Unit

Propagation Delay

1

3

nS

Output Rise Time

(Measured from 0.8V to 2V)

1.5

nS

Output Fall Time

(Measured from 2V to 0.8V)

1.5

nS

Same device output pin to pin skew

5

270

pS

Pulse skew

6,9

270

pS

Part to part skew

7

550

pS

Output Enable Time

OE

5.2

nS

Output Disable Time

OE

5.2

nS

Input Frequency

f ≤133MHz

133

MHz

Propagation Delay

0.5

2.5

nS

Output Rise Time

(Measured from 0.7V to 1.7V)

1.25

nS

Output Fall Time

(Measured from 1.7V to 0.7V)

1.25

nS

Same device output pin to pin skew

5

200

pS

Pulse skew

6,9

270

pS

Part to part skew

7

550

pS

Output Enable Time

OE

5.2

nS

Output Disable Time

OE

5.2

nS

Input Frequency

133MHz ≤ f ≤166MHz

166

MHz

Notes:

1. See test circuits and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

imply skew.

5. Skew measured between all outputs under identical transitions and load conditions.

8. Airflow of 1m/s is recommended for frequencies above 133MHz.

9. This parameter is measured using f = 1MHz.