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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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MPC5604B Arkusz danych(PDF) 44 Page - Freescale Semiconductor, Inc |
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MPC5604B Arkusz danych(HTML) 44 Page - Freescale Semiconductor, Inc |
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44 / 72 page  MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 Electrical characteristics Freescale Semiconductor 44 4.18.2 DSPI characteristics Table 39. DSPI characteristics No. Symbol C Parameter Value Unit Min Typ Max 1 tSCK SR D SCK cycle time 64 — — ns — fDSPI SR D DSPI digital controller frequency — — fCPU MHz — Δt CSC CC D Internal delay between pad associated to SCK and pad associated to CSn in master mode — — 1201 1 Maximum is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM pad. ns 2 tCSCext 2 2 The t CSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than Δt CSC to ensure positive tCSCext. CC D CS to SCK delay Master mode tCSCext = tCSC + ΔtCSC ns SR D Slave mode 32 — — 3 tASCext 3 3 The t ASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than Δt ASC to ensure positive tASCext. CC D After SCK delay Master mode tASCext = tASC + ΔtCSC ns SR D Slave mode 1/fDSPI + 5 ns — — ns 4 tSDC CC D SCK duty cycle Master mode — tSCK/2 — ns SR D Slave mode tSCK/2 — — 5 tA SR D Slave access time — 27 — — ns 6 tDI SR D Slave SOUT disable time — 0 — — ns 7 tSUI SR D Data setup time for inputs Master (MTFE = 0) 35 — — ns Slave 5 — — Master (MTFE = 1) 35 — — 8 tHI SR D Data hold time for inputs Master (MTFE = 0) 0 — — ns Slave 24 4 This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register. — — Master (MTFE = 1) 0 — — 9 tSUO 5 5 SCK and SOUT configured as MEDIUM pad CC D Data valid after SCK edge Master (MTFE = 0) — — 32 ns Slave — — 34 Master (MTFE = 1) — — 32 10 tHO (5) CC D Data hold time for outputs Master (MTFE = 0) 2 — — ns Slave 5.5 — — Master (MTFE = 1) 2 — — |
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