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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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ATmega16 Arkusz danych(PDF) 88 Page - ATMEL Corporation |
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ATmega16 Arkusz danych(HTML) 88 Page - ATMEL Corporation |
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88 / 357 page  88 2466S–AVR–05/09 ATmega16(L) sampling, the maximum frequency of an external clock it can detect is half the sampling fre- quency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than f clk_I/O/2.5. An external clock source can not be prescaled. Figure 39. Prescaler for Timer/Counter0 and Timer/Counter1 (1) Note: 1. The synchronization logic on the input pins ( T1/T0) is shown in Figure 38. Special Function IO Register – SFIOR • Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0 When this bit is written to one, the Timer/Counter1 and Timer/Counter0 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. This bit will always be read as zero. PSR10 Clear clk T1 clk T0 T1 T0 clk I/O Synchronization Synchronization Bit 7 6 5 4 3 2 1 0 ADTS2 ADTS1 ADTS0 – ACME PUD PSR2 PSR10 SFIOR Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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