WM8146

Product Preview

WOLFSON MICROELECTRONICS LTD

PP Rev 1.1 January 2000

8

TIMING

Figure 6 illustrates the use of the RLC pin, MCLK and VSMP to control the timing of the CL pulse for

a typical CCD waveform. The CL pulse is applied during the reset period.

The input signal applied to the RLC pin is sampled on the positive edge of MCLK that occurs during

each VSMP pulse. The sampled level, high (or low) controls the presence (or absence) of the internal

CL pulse on the next reset level. The position of CL can be adjusted by using control bits

CDSREF[1:0], as shown in Figure 7.

The VRLC pin outputs the analogue RLC voltage selected via control set-up register 3 bits RLC[1:0].

MCLK

VSMP

RLC

CL

(CDSREF = 01)

INPUT VIDEO

1X

X

0

X

X

0

RGB

RGB

No RLC on this Pixel

RLC on this Pixel

Programmable Delay

RGB

Figure 6 Relationship of RLC Pin, MCLK and VSMP to Internal Clamp Pulse, CL

CDS/NON-CDS PROCESSING

For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel

common mode noise. For CDS operation, the video level is processed with respect to the video reset

level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must

be set to 1 (default), this controls switch 2 (Figure 5) and causes the signal reference to come from

programming control bits CDSREF[1:0], as shown in Figure 7 .

For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed

with respect to the reference voltage VMID.

MCLK

VSMP

VS

R

R

R

R

Figure 7 Reset Sample and Clamp Timing