WM8148 datasheet(21/43 Pages) WOLFSON

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WM8148

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 4.0 April 1999

OP[11:4]

MUXOP=1

OP[11:0]

MUXOP=0

Figure 21 Output Data for 2 x 8-bit and 12 bit Output.

Where:

A = < d11, d10, d9, d8, d7, d6, d5, d4 >

B = < d3, d2, d1, d0, TVIOL, CC[1], CC[0], OVRNG >

C = < d11, d10, … d1, d0 >

COLOUR CODE BITS

CC[1]

CC[0]

CHANNEL

Red

Green

Blue

Table 3 Colour Code Bits CC[1:0]

ERROR FLAGS

The two error flags are:

TVIOL: This goes high if the reset sample and clamp positions set up in bits RESREF[3:0], are

inconsistent with the selected mode of operation.

OVRNG: This goes high if the input to the ADC exceeds its input range.

These flags are output in byte B of multiplexed-mode parallel output data as above. Each is also

available via the SDO pin if so configured via the SDO[1:0] register bits.

LATENCY

Default latency from the last rising edge of MCLK during the VSMP pulse to data output depends on

the chosen Input Sampling Mode. To align pixel outputs with post processing circuitry and to reduce

interaction with video sampling instances, the latency through the WM8148 device can be adjusted

by Control bits DEL[1:0] and FDEL[1:0].

DIGITAL MANAGEMENT INTERFACE (DMI)

The DMI is used to write contents to and read back contents from the internal registers in either serial

or parallel mode. The PNS pin is tied low for serial and high for parallel mode.

SERIAL INTERFACE

SCK

SEN

SDI

a 5

a 3a 2a 1a 0b 7b 6b 5b 4b 3b 2b 1b 0

Address

Data Word

Figure 22 Serial Interface Register Write

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