LPC2921 datasheet(21/84 Pages) NXP

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LPC2921_23_25_3

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Product data sheet

Rev. 03 — 14 April 2010

21 of 84

NXP Semiconductors

LPC2921/2923/2925

ARM9 microcontroller with CAN, LIN, and USB

The USB device controller has the following features:

• Fully compliant with USB 2.0 specification (full speed).

• Supports 32 physical (16 logical) endpoints with a 2 kB endpoint buffer RAM.

• Supports Control, Bulk, Interrupt and Isochronous endpoints.

• Scalable realization of endpoints at run time.

• Endpoint Maximum packet size selection (up to USB maximum specification) by

software at run time.

• Supports SoftConnect and GoodLink features.

• While USB is in the Suspend mode, the LPC2921/2923/2925 can enter the reduced

power mode and wake up on USB activity.

• Supports DMA transfers with the on-chip SRAM blocks on all non-control endpoints.

• Allows dynamic switching between CPU-controlled slave and DMA modes.

• Double buffer implementation for Bulk and Isochronous endpoints.

6.10.2 Pin description

6.10.3 Clock description

Access to the USB registers is clocked by the CLK_SYS_USB, derived from

BASE_SYS_CLK, see Section 6.7.2. The CGU1 provides an independent base clock to

the USB block, BASE_USB_CLK (see Section 6.15.3).

Table 11.

USB device port pins

Pin name

Direction

Description

USB_VBUS

USB_VBUS status input. When this function is not enabled

via its corresponding PINSEL register, it is driven HIGH

internally.

USB_D+

I/O

positive differential data

USB_D

−

I/O

negative differential data

USB_CONNECT

SoftConnect control signal

USB_UP_LED

GoodLink LED control signal

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