LPC2921 datasheet(49/84 Pages) NXP

49 / 84 page

LPC2921_23_25_3

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 03 — 14 April 2010

49 of 84

NXP Semiconductors

LPC2921/2923/2925

ARM9 microcontroller with CAN, LIN, and USB

6.15.5 Power Management Unit (PMU)

This module enables software to actively control the system’s power consumption by

disabling clocks not required in a particular operating mode.

Using the base clocks from the CGU as input, the PMU generates branch clocks to the

rest of the LPC2921/2923/2925. Output clocks branched from the same base clock are

phase- and frequency-related. These branch clocks can be individually controlled by

software programming.

The key features are:

• Individual clock control for all LPC2921/2923/2925 sub-modules.

• Activates sleeping clocks when a wake-up event is detected.

• Clocks can be individually disabled by software.

• Supports AHB master-disable protocol when AUTO mode is set.

• Disables wake-up of enabled clocks when Power-down mode is set.

• Activates wake-up of enabled clocks when a wake-up event is received.

• Status register is available to indicate if an input base clock can be safely switched off

(i.e. all branch clocks are disabled).

6.15.5.1

Functional description

The PMU controls all internal clocks coming out of the CGU0 for power-mode

management. With some exceptions, each branch clock can be switched on or off

individually under control of software register bits located in its individual configuration

Table 29 shows which mode-control bits are supported by each branch clock.

By programming the configuration register the user can control which clocks are switched

on or off, and which clocks are switched off when entering Power-down mode.

Note that the standby-wait-for-interrupt instructions of the ARM968E-S processor (putting

the ARM CPU into a low-power state) are not supported. Instead putting the ARM CPU

into power-down should be controlled by disabling the branch clock for the CPU.

Remark: For any disabled branch clocks to be re-activated their corresponding base

clocks must be running (controlled by the CGU0).

Table 29 shows the relation between branch and base clocks, see also Section 6.7.1.

Every branch clock is related to one particular base clock: it is not possible to switch the

source of a branch clock in the PMU.

Table 28.

RGU pins

Symbol

Direction

Description

RST

external reset input, active LOW; pulled up internally

LPC2921 Arkusz danych(PDF) 49 Page - NXP Semiconductors

LPC2921 Arkusz danych(HTML) 49 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

Arkusz danych Pobierz

Link URL