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SDIP-38L Arkusz danych(PDF) 14 Page - STMicroelectronics |
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SDIP-38L Arkusz danych(HTML) 14 Page - STMicroelectronics |
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14 / 21 page ![]() Electrical characteristics STGIPL14K60 14/21 Doc ID 15589 Rev 3 3.2 Waveforms definitions Figure 8. Dead time and interlocking waveforms definitions LIN HIN LVG HVG LIN HIN LVG HVG LIN HIN LVG HVG LIN HIN LVG HVG DTLH DTHL DTLH DTHL DTLH DTHL DTLH DTHL gate driver outputs OFF (HALF-BRIDGE TRI-STATE) CONTROL SIGNAL EDGES OVERLAPPED: INTERLOCKING + DEAD TIME CONTROL SIGNALS EDGES SYNCHRONOUS (*): DEAD TIME CONTROL SIGNALS EDGES NOT OVERLAPPED, BUT INSIDE THE DEAD TIME: DEAD TIME CONTROL SIGNALS EDGES NOT OVERLAPPED, OUTSIDE THE DEAD TIME: DIRECT DRIVING (*) HIN and LIN can be connected together and driven by just one control signal gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) |
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