SC2441AEVB datasheet(18/37 Pages) SEMTECH

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 2006 Semtech Corp.

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POWER MANAGEMENT

SC2441A

minimum locking frequencies of the slave should be

selected to accommodate the variation in the master’s

frequency. Phase shift between the master and the slave

can be programmed with an optional resistor (Figure 5).

More detailed discussion can be found in the Application

Information.

Pulling the

SHDN

SYNC/

pin below 0.5V shuts off the

SC2441A after 85

µs time delay.

Control Loop

The step-down controllers and the boost regulator in the

SC2441A use peak current-mode control for fast transient

response and current sharing in single output operation.

Current-mode switching regulators utilize a dual-loop

feedback control system. The error amplifier output controls

the peak inductor current of that channel. This is the inner

current loop. The double reactive poles of the output LC

filter are reduced to a single real pole by the inner current

loop, easing loop compensation. Fast transient response

can be obtained with a simple Type-2 compensation

network. In the outer loop, the error amplifier regulates

the output voltage.

Referring to the block diagrams in Figures 2 and 3, the

sensed inductor current is summed with the slope-

compensating ramp before compared to the output of the

error amplifier. The PWM comparator trip point determines

the switch turn-on pulse width. The current-limit comparator

ILIM turns off the power switch when the sensed current

exceeds the corresponding current-limit threshold. ILIM

therefore provides cycle-by-cycle current limit. All three

converters in the SC2441A have internal ramp-

compensation to prevent sub-harmonic oscillation when

operating above 50% duty cycle. The internal compensating

ramp is designed for an inductor ripple-current between

and

of the maximum inductor current and the peak-

to-peak current-sense voltage (CSP-CSN of the step-down

controllers) between

and

of the current-limit

threshold (25mV). The current-limits of all three

converters are unaffected by the compensation ramps.

Current-Sensing

The inductor current needs to be sensed for use as PWM

modulating ramp. Either sense resistor or inductor series

resistance (DCR) can be used as the sensing element for

the step-down controllers. Since the maximum current-

sense voltage (CSP-CSN) is only 25mV, a precision sense

resistor in series with the inductor can be used at the output

without resulting in excessive power dissipation.

Alternatively the DCR of the inductor can also be used.

Both methods are less sensitive to supply and ground

transients than high-side or low-side sensing because the

sensed voltage is developed at the output of the step-

down converter. DCR sensing will be described in more

details in the Applications Information section.

Boost switch current is sensed with an integrated sense

resistor with a minimum current-limit of 0.6A.

Error Amplifiers

All error amplifiers in the SC2441A are of transconductance

type. Converters are compensated with series RC network

from the COMP pins to the ground. An additional small

parallel capacitor may be required for stability.

In Figure 2 the error amplifiers EA1 and EA2 are shown

with two non-inverting inputs. The non-inverting input with

lower voltage predominates. One positive input is biased

to a 0.5V precision reference. The other non-inverting input

of the error amplifier is tied to a voltage equal to

(VSS/EN - 1.25V)/3.

During converter start up, the effective positive input of

the error amplifier stays at 0 until the soft-start capacitor

at the SS/EN pin is charged above 1.25V. The

corresponding COMP pin is also pulled low by the

comparator A

2 or A3. After the SS/EN voltage exceeds

1.25V, the COMP pin is released. Both the upper and the

lower gate drives remain low until the COMP voltage

exceeds 1.85V. If the soft-start capacitor charging time

is sufficiently long, then both the FB and the output

voltage will track the divided SS/EN voltage on their way

to regulation. If the starting output voltage is non-zero,

then the COMP voltage and the corresponding gate drives

will remain low until the divided SS/EN voltage exceeds

the feedback voltage. Starting into a pre-existing output

is seamless.

Operation (Cont.)

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