SC2441AEVB datasheet(25/37 Pages) SEMTECH

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POWER MANAGEMENT

SC2441A

Pre-biased Start Up

Sometimes the step-down converter is to start into a

pre-biased output load. The pre-biased voltage is normally

lower than the output setpoint of the step-down

converter.

As described earlier, pre-bias startup process with the

SC2441A is seamless. The testing setup of the pre-biased

start-up is shown as in Figure 14.

Blocking Diode

External

Voltage

Source

Module

under

Test

LOAD

Figure 14. Test Setup for Pre-biased Start Up

Applications Information

In Figure 14, V

S is the external power supply pre-biasing

O. D1 blocks the output of the power module under test

from V

S during soft-start. RLOAD is the resistive load of the

module under test. Before power-up the module, monitor

O to ensure that it is the desired pre-biased output

voltage. Then power-up the module. V

O should rise

smoothly.

Free-running Operation

The internal oscillator of the SC2441A can either free-

run or it can be phase-locked to an external clock.

In free-running mode, the internal phase-locked loop is

disabled by tying an external resistor from the PLLF pin

to V

IN. The external resistor ROSC (see figure 5(a))

programs the channel frequency. The PLLF pull-up resistor

should be carefully selected so that the voltage at the

PLLF pin is above 1V. A value between 20K

Ω to 50KΩ is

recommended.

Pull-up resistor can also be tied to V

CC if VCC is present

before the SC2441A starts to switch. The advantage tying

the pull-up resistor to V

CC is because that the VCC is a

regulated output from either a boost converter or a sepic

converter. The resistor from the PLLF pin can be tied to

CC if VCC is from a boost converter output. The reason is

that the V

CC will be powered up from the input VIN before

output of the boost converter reaches the setpoint.

However, in some applications, a SEPIC converter is

employed to get stable V

CC due to the wide input voltage

range. In this case, the resistor from the PLLF pin should

not be connected to the V

CC due to the presence of a DC

blocking capacitor in the converter. The SC2441A will not

switch if the PLLF pin is at zero volt.

Applying more than 2.1V at the PLLF pin activates the

diode clamp circuit (see Figure 5(a)). The filtering

components (R

1,R2, C1 and C2 in Figure 5(a)) are not

needed while free-running. The clamp activation will have

no effect on the PLL if V

PLLF >1V.

The internal clock is brought out to the CKOUT pin. The

signal at CKOUT pin can be used as the synchronizing

clock for other SC2441As in a master-slave configuration.

0.25ms

1 =

25mV

28A

)

(

)

(

With an arbitrary selection of

3.01K

, we can

get C

1=83nF. Since 83nF is not a standard capacitance

value, we use 100nF capacitor for C

1. Consequently,

2.5

. And we can also derive:

25mV

28A

2.5K

= 6.80K

= 3.92K

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