AD9552PCBZ datasheet(15/32 Pages) AD

15 / 32 page

AD9552

Rev. C | Page 15 of 32

VCO Frequency (MHz)

Output (MHz)

3536.763

657.421875 × (255/237)

3582.686

716.5372

3593.75

718.75

3598.672

719.7344

3740.355

748.0709

3750

750

3888

777.6

3897.843

779.5686

3906.25

781.25

4028.32

625 × (10/8) × (66/64)

Reference Monitor

COMPONENT BLOCKS

The REF input includes a monitor circuit that detects signal

presence at the REF input. If the device detects a clock signal on

the REF pin, it automatically selects the REF input as the input

reference source and shuts down the crystal oscillator. This auto-

matic preference for a REF input signal is the default mode of

operation. However, the user can override the default setting via

signal detector associated with the REF input and activates the

crystal oscillator (whether or not a REF input signal is present).

Input Reference

The AD9552 offers the following input reference options:

•

Crystal resonator connected directly across the XTAL pins

•

CMOS-compatible, single-ended clock source connected

directly to the REF pin

In the case of a crystal resonator, the AD9552 expects a crystal

with a specified load capacitance of 15 pF (default). The

AD9552 provides the load capacitance internally. The internal

load capacitance consists of a fixed component of 13 pF and a

variable (programmable) component of 0 pF to 15.75 pF.

2× Frequency Multiplier

The 2× frequency multiplier provides the option to double

the frequency delivered by either the REF or XTAL input. This

allows the user to take advantage of a higher frequency deli-

vered to the PLL, which allows for greater separation between

the frequency generated by the PLL and the associated reference

spur. However, increased reference spur separation comes at the

expense of the harmonic spurs introduced by the frequency

multiplier. As such, beneficial use of the frequency multiplier

is application specific.

After applying power to the AD9552 (or after a device reset),

the programmable component assumes a value of 2 pF. This

establishes the default load capacitance of 15 pF.

To accommodate crystals with a specified load capacitance other

than 15 pF (8 pF to 23.75 pF), the user can adjust the program-

mable capacitance in 0.25 pF increments via Register 0x1B[5:0].

Note that when the user sets Register 0x1B[7] to 0 (enabling SPI

control of the XTAL tuning capacitors), the variable capacitance

changes from 2 pF (its power-up value) to 15.75 pF due to the

default value of Register 0x1B[5:0]. This causes the crystal load

capacitance to be 23.75 pF until the user overwrites the default

contents of Register 0x1B[5:0].

PLL

The PLL consists of a phase/frequency detector (PFD), a

partially integrated analog loop filter (see Figure 20), an

integrated voltage-controlled oscillator (VCO), and a

feedback divider with an optional third-order SDM that

allows for fractional divide ratios. The PLL produces a

nominal 3.7 GHz signal that is phase-locked to the input

reference signal.

A noncomprehensive, alphabetical list of crystal manufacturers

includes the following:

•

AVX/Kyocera

•

ECS

The loop bandwidth of the PLL is nominally 50 kHz. The PFD of

the PLL drives a charge pump that automatically changes current

proportionately to the feedback divider value. This increase or

decrease in current maintains a constant loop bandwidth with

changes in the input reference or the output frequency.

•

Epson Toyocom

•

Fox Electronics

•

NDK

•

Siward

The AD9552 evaluation board functions with the NDK

NX3225SA crystal or with the Siward 571200-A258-001 crystal.

Although these crystals meet the load capacitance and motional

resistance requirements of the AD9552 according to their data

sheets, Analog Devices, Inc., does not guarantee their operation

with the AD9552, nor does Analog Devices endorse one supplier

of crystals over another.

EXTERNAL

LOOP FILTER

CAPACITOR

2.5k

Ω

1.25k

Ω

1.25k

Ω

2.5k

Ω

105pF

15pF

20pF

FROM

CHARGE

PUMP

VCO

Figure 20. Internal Loop Filter

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