AD9552PCBZ datasheet(25/32 Pages) AD

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AD9552

Rev. C | Page 25 of 32

PLL Charge Pump and PFD Control (Register 0x0A to Register 0x0D)

Table 19.

Address

Bit

Bit Name

Description

0x0A

[7:0]

Charge pump current control

These bits set the magnitude of the PLL charge pump current. The granularity is

~3.5 μA with a full-scale magnitude of ~900 μA. Register 0x0A is ineffective unless

0x0B

Enable SPI control of charge

pump current

Controls functionality of Register 0x0A.

0 = the device automatically controls the charge pump current (default).

1 = charge pump current defined by Register 0x0A.

Enable SPI control of

antibacklash period

Controls functionality of Register 0x0D[7:6].

0 = the device automatically controls the antibacklash period (default).

1 = antibacklash period defined by Register 0x0D[7:6].

[5:4]

CP mode

Controls the mode of the PLL charge pump.

00 = tristate.

01 = pump up.

10 = pump down.

11 = normal (default).

Enable CP mode control

Controls functionality of Bits[5:4] (CP mode).

0 = the device automatically controls the charge pump mode (default).

1 = charge pump mode is defined by Bits[5:4].

PFD feedback input edge control

Selects the polarity of the active edge of the PLL’s feedback input.

0 = positive edge (default).

1 = negative edge.

PFD reference input edge control

Selects the polarity of the active edge of the PLL’s reference input.

0 = positive edge (default).

1 = negative edge.

Force VCO to midpoint frequency

Selects VCO control voltage functionality.

0 = normal VCO operation (default).

1 = force VCO control voltage to midscale.

0x0C

Unused

Unused.

CP offset current polarity

Selects the polarity of the charge pump offset current of the PLL. This bit is ineffective

unless Bit 3 = 1.

0 = pump up (default).

1 = pump down.

[5:4]

CP offset current

Controls the magnitude of the charge pump offset current of the PLL as a fraction of

the value in Register 0x0A. This bit is ineffective unless Bit 3 = 1.

00 = 1/2 (default).

01 = 1/4.

10 = 1/8.

11 = 1/16.

Enable CP offset current control

Controls functionality of Bits[6:4].

0 = the device automatically controls charge pump offset current (default).

1 = charge pump offset current defined by Bits[6:4].

2:0

Reserved

0x0D

[7:6]

Antibacklash control

Controls the PFD antibacklash period of the PLL. These bits are ineffective unless

00 = minimum (default).

01 = low.

10 = high.

11 = maximum.

[5:1]

Unused

Unused.

PLL lock detector power-down

Controls power-down of the PLL lock detector.

0 = lock detector active (default).

1 = lock detector powered down.

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