430 datasheet(18/71 Pages) INTEL

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Electrical Specifications

Datasheet

3.3.1

VCC Decoupling

Regulator solutions need to provide bulk capacitance with a low effective series

resistance (ESR) and keep a low interconnect resistance from the regulator to the

socket. Bulk decoupling for the large current swings when the part is powering on, or

entering/exiting low-power states, must be provided by the voltage regulator solution.

It is strongly recommended that the layout and decoupling recommendations be

followed - for more details, contact your Intel representative.

3.3.2

FSB AGTL+ Decoupling

Celeron M processors integrate signal termination on the die as well as incorporate high

frequency decoupling capacitance on the processor package. Decoupling must also be

provided by the system motherboard for proper AGTL+ bus operation. For more

information, contact your Intel representative.

3.3.3

FSB Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the

processor. As in previous generation processors, the Celeron M processor core

frequency is a multiple of the BCLK[1:0] frequency. The Celeron M processor bus ratio

multiplier will be set at its default ratio at manufacturing. The Celeron M processor uses

a differential clocking implementation. For more information on Celeron M processor

clocking, contact your Intel representative.

3.4

Voltage Identification and Power Sequencing

Information regarding the VID specification for the Celeron M processor is available

from your Intel representative.

The Celeron M processor uses seven voltage identification pins, VID[6:0], to support

automatic selection of power supply voltages. The VID pins for Celeron M processor are

CMOS outputs driven by the processor VID circuitry. Table 2 specifies the voltage level

corresponding to the state of VID[6:0]. For more details about VR design to support the

Celeron M processor power supply requirements, please contact your Intel

representative.

Power source characteristics must be stable whenever the supply to the voltage

regulator is stable. Refer to the Figure 3 for timing details of the power-up sequence.

Figure 4 shows the power-down sequencing requirements.

430 Arkusz danych(PDF) 18 Page - Intel Corporation