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Datasheet

Electrical Specifications

3.7

FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock

(BCLK[1:0]). These signals should be connected to the clock chip and Intel 945GMS

and 940GML Express Chipsets on the platform. The BSEL encoding for BCLK[1:0] is

shown in Table 3.

3.8

FSB Signal Groups

In order to simplify the following discussion, the FSB signals have been combined into

groups by buffer type. AGTL+ input signals have differential input buffers, which use

GTLREF as a reference level. In this document, the term “AGTL+ Input” refers to the

AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+

Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when

driving.

With the implementation of a source synchronous data bus comes the need to specify

two sets of timing parameters. One set is for common clock signals which are

dependant upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second

set is for the source synchronous signals which are relative to their respective strobe

lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are

still present (A20M#, IGNNE#, etc.) and can become active at any time during the

clock cycle. Table 4 identifies which signals are common clock, source synchronous,

and asynchronous.

Table 3.

BSEL[2:0] Encoding for BCLK Frequency

BSEL[2]

BSEL[1]

BSEL[0]

BCLK

Frequency

LLL

RESERVED

133 MHz

LHL

RESERVED

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