MPC5675K datasheet(83/140 Pages) FREESCALE

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Electrical characteristics

MPC5675K Microcontroller Data Sheet, Rev. 4

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

A second aspect involving the capacitance network shall be considered. Assuming the three capacitances

CF, CP1, and CP2 are initially charged at the source voltage VA (please see the equivalent circuit in

Figure 10): A charge sharing phenomenon is installed when the sampling phase is started (A/D switch is

closed).

Figure 11. Transient behavior during sampling phase

In particular two different transient periods can be distinguished:

•

A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling

capacitance CS occurs (CS is supposed initially completely discharged): considering a worst case

(since the time constant in reality would be faster) in which CP2 is reported in parallel to CP1 (call

CP = CP1 + CP2), the two capacitances CP and CS are in series, and the time constant is:

Eqn. 12

Equation 12 can again be simplified considering only CS as an additional worst condition. In

reality, the transient is faster, but the A/D converter circuitry has been designed to be robust also in

the very worst case: the sampling time TS is always much longer than the internal time constant:

Eqn. 13

The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1

on the capacitance according to Equation 14:

Eqn. 14

•

A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance)

through the resistance RL: again considering the worst case in which CP2 and CS were in parallel

to CP1 (since the time constant in reality would be faster), the time constant is:

Eqn. 15

In this case, the time constant depends on the external circuit: in particular imposing that the

transient is completed well before the end of sampling time TS, a constraints on RL sizing is

obtained:

VA1

VA2

VCS

Voltage Transient on CS

V <0.5 LSB





1 < (RSW + RAD) CS << TS



2 = RL (CS + CP1 + CP2)

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