ADP5033ACBZ-1-R7 datasheet(16/28 Pages) AD

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ADP5033

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witching losses are associated with the current drawn by the

(10)

whe

the P-MOSFET gate capacitance.

E-N

) is approxi-

osses occur because the P-channel power

× (tRISE + tFALL) × fSW

(11)

whe

fall time of the

s of

d parameters are used for estimat-

Dissipation

ven by

)

(12)

whe

he load current of the LDO regulator.

e LDO,

all, and it

driver to turn on and turn off the power devices at the switching

frequency. The amount of switching power loss is given by

PSW = (CGATE-P + CGATE-N) × VIN12 × fSW

re:

CGATE-P is

CGATE-N is the N-MOSFET gate capacitance.

For the ADP5033, the total of (CGATE-P + CGAT

mately 150 pF.

The transition l

MOSFET cannot be turned on or off instantaneously, and t

SW node takes some time to slew from near ground to near

VOUT1 (and from VOUT1 to ground). The amount of transition

loss is calculated by

PTRAN = VIN1 × IOU

re tRISE and tFALL are the rise time and the

switching node, SW. For the ADP5033, the rise and fall time

SW are in the order of 5 ns.

If the preceding equations an

ing the converter efficiency, it must be noted that the equations

do not describe all of the converter losses, and the parameter

values given are typical numbers. The converter performance

also depends on the choice of passive components and board

layout; therefore, a sufficient safety margin should be included

in the estimate.

LDO Regulator Power

The power loss of a LDO regulator is gi

PDLDO = [(VIN − VOUT) × ILOAD] + (VIN × IGND

re:

ILOAD is t

VIN and VOUT are input and output voltages of th

respectively.

IGND is the ground current of the LDO regulator.

Power dissipation due to the ground current is sm

can be ignored.

JUNCTION TEMPERATURE

The total power dissipation in the ADP5033 simplifies to

PD = PDBUCK + PDLDO1 + PDLDO2

(13)

In cases where the board temperature TA is known, the thermal

resistance parameter, θJA, can be used to estimate the junction

temperature rise. TJ is calculated from TA and PD using the

formula

TJ = TA + (PD × θJA)

(14)

The typical θJA value for the 16-ball, 0.5 mm pitch WLCSP is

57°C/W (see Table 6). A very important factor to consider is

that θJA is based on a 4-layer 4 in × 3 in, 2.5 oz copper, as per

JEDEC standard, and real applications may use different sizes

and layers. It is important to maximize the copper used to remove

the heat from the device. Copper exposed to air dissipates heat

better than copper used in the inner layers. The exposed pad

should be connected to the ground plane with several vias.

If the case temperature can be measured, the junction tempera-

ture is calculated by

TJ = TC + (PD × ΨJB)

(15)

where TC is the case temperature and ΨJB is the junction-to-

board thermal resistance provided in Table 6.

When designing an application for a particular ambient

temperature range, calculate the expected ADP5033 power

dissipation (PD) due to the losses of all channels by using the

Equation 8 to Equation 13. From this power calculation, the

junction temperature, TJ, can be estimated using Equation 14.

The reliable operation of the converter and the two LDO regulators

can be achieved only if the estimated die junction temperature of

the ADP5033 (Equation 14) is less than 125°C. Reliability and

mean time between failures (MTBF) is highly affected by increas-

ing the junction temperature. Additional information about

product reliability can be found in the ADI Reliability Handbook,

which can be found at www.analog.com/reliability_handbook.

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