AFS090 datasheet(31/334 Pages) MICROSEMI

Numer części	AFS090

Szczegółowy opis	Fusion Family of Mixed Signal FPGAs

PDF	334 Pages

Scroll/Zoom	100%

Producent	MICROSEMI [Microsemi Corporation]

Strona internetowa	http://www.microsemi.com

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Fusion Family of Mixed Signal FPGAs

R e visio n 2

2 - 15

Clock Aggregation

Clock aggregation allows for multi-spine clock domains. A MUX tree provides the necessary flexibility to

allow long lines or I/Os to access domains of one, two, or four global spines. Signal access to the clock

aggregation system is achieved through long-line resources in the central rib, and also through local

resources in the north and south ribs, allowing I/Os to feed directly into the clock system. As Figure 2-14

indicates, this access system is contiguous.

There is no break in the middle of the chip for north and south I/O VersaNet access. This is different from

the quadrant clocks, located in these ribs, which only reach the middle of the rib. Refer to the Using

Global Resources in Actel Fusion Devices

application note.

Figure 2-14 • Clock Aggregation Tree Architecture

Global Spine

Global Rib

Global Driver and MUX

I/O Access

Internal Signal Access

I/O Tiles

Global Signal Access

Tree Node MUX

AFS090 Arkusz danych(PDF) 31 Page - Microsemi Corporation