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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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AFS090 Arkusz danych(PDF) 33 Page - Microsemi Corporation |
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AFS090 Arkusz danych(HTML) 33 Page - Microsemi Corporation |
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33 / 334 page  Fusion Family of Mixed Signal FPGAs R e visio n 2 2 - 17 VersaNet Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are dependent upon I/O standard, and the clock may be driven and conditioned internally by the CCC module. Table 2-5, Table 2-6, Table 2-7, and Table 2-8 on page 2-18 present minimum and maximum global clock delays within the device Minimum and maximum delays are measured with minimum and maximum loading, respectively. Timing Characteristics Table 2-5 • AFS1500 Global Resource Timing Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 tRCKL Input Low Delay for Global Clock 1.53 1.75 1.74 1.99 2.05 2.34 ns tRCKH Input High Delay for Global Clock 1.53 1.79 1.75 2.04 2.05 2.40 ns tRCKMPWH Minimum Pulse Width High for Global Clock ns tRCKMPWL Minimum Pulse Width Low for Global Clock ns tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.34 ns FRMAX Maximum Frequency for Global Clock MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9. Table 2-6 • AFS600 Global Resource Timing Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 tRCKL Input Low Delay for Global Clock 1.27 1.49 1.44 1.70 1.69 2.00 ns tRCKH Input High Delay for Global Clock 1.26 1.54 1.44 1.75 1.69 2.06 ns tRCKMPWH Minimum Pulse Width High for Global Clock ns tRCKMPWL Minimum Pulse Width Low for Global Clock ns tRCKSW Maximum Skew for Global Clock 0.27 0.31 0.36 ns FRMAX Maximum Frequency for Global Clock MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9. |
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