AFS090 datasheet(101/334 Pages) MICROSEMI

101 / 334 page

Fusion Family of Mixed Signal FPGAs

R e visio n 2

2 - 85

The Analog Quad offers a wide variety of prescaling options to enable the ADC to resolve the input

signals. Figure 2-65 shows the path through the Analog Quad for a signal that is to be prescaled prior to

conversion. The ADC internal reference voltage and the prescaler factors were selected to make both

prescaling and postscaling of the signals easy binary calculations (refer to Table 2-57 on page 2-132 for

details). When an analog input pad is configured with a prescaler, there will be a 1 M

Ω resistor to ground.

This occurs even when the device is in power-down mode. In low power standby or sleep mode (VCC is

OFF, VCC33A is ON, VCCI is ON) or when the resource is not used, analog inputs are pulled down to

ground through a 1 M

Ω resistor. The gate driver output is floating (or tristated), and there is no extra

current on VCC33A.

These scaling factors hold true whether the particular pad is configured to accept a positive or negative

voltage. Note that whereas the AV and AC pads support the same prescaling factors, the AT pad

supports a reduced set of prescaling factors and supports positive voltages only.

Typical scaling factors are given in Table 2-57 on page 2-132, and the gain error (which contributes to the

minimum and maximum) is in Table 2-49 on page 2-119.

Figure 2-65 • Analog Quad Prescaler Input Configuration

Prescaler

Analog Quad

Voltage

Monitor Block

Current

Monitor Block

Digital

Input

Power

MOSFET

Gate Driver

Current

Monitor / Instr

Amplifier

Temperature

Monitor

Digital

Input

Digital

Input

Pads

To Analog MUX

To FPGA

(DAVOUTx)

To FPGA

(DACOUTx)

To FPGA

(DATOUTx)

On-Chip

Gate

Driver

Temperature

Monitor Block

Off-Chip

From FPGA

(GDONx)

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