AD9737ABBCZ datasheet(41/64 Pages) AD

41 / 64 page

Data Sheet

AD9737A/AD9739A

Rev. | Page 41 of 64

The AD9737A/AD9739A serial port can support both most

significant bit (MSB) first and least significant bit (LSB) first

data formats. Figure 153 illustrates how the serial port words

are formed for the MSB first and LSB first modes. The bit order

is controlled by the LSB/MSB bit (Register 0x00, Bit 6). The

default value of Bit 6 is 0, MSB first. When the LSB/MSB bit is

set high, the serial port interprets both instruction and data bytes

LSB first.

SCLK

SDATA

SCLK

SDATA

R/W

D71

D01 D11

D6N D7N

D61

D1N D0N

DATA TRANSFER CYCLE

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

INSTRUCTION CYCLE

Figure 153. SPI Timing, MSB First (Upper) and LSB First (Lower)

Figure 154 illustrates the timing requirements for a write

operation to the SPI port. After the serial port enable (CS)

signal goes low, data (SDIO) pertaining to the instruction

header is read on the rising edges of the clock (SCLK). To

initiate a write operation, the read/not-write bit is set low. After

the instruction header is read, the eight data bits pertaining to

the specified register are shifted into the SDIO pin on the rising

edge of the next eight clock cycles.

Figure 155 illustrates the timing for a 3-wire read operation to

the SPI port. After CS goes low, data (SDIO) pertaining to the

instruction header is read on the rising edges of SCLK. A read

operation occurs if the read/not-write indicator is set high. After

the address bits of the instruction header are read, the eight data

bits pertaining to the specified register are shifted out of the

SDIO pin on the falling edges of the next eight clock cycles.

Figure 156 illustrates the timing for a 4-wire read operation to

the SPI port. The timing is similar to the 3-wire read operation

with the exception that data appears at the SDO pin only, whereas

the SDIO pin remains at high impedance throughout the

operation. The SDO pin is an active output only during the data

transfer phase and remains three-stated at all other times.

SCLK

SDIO

fSCLK

tLOW

tHI

tDS

tDH

R/W

Figure 154. SPI Write Operation Timing

SCLK

SDIO

fSCLK

tLOW

tHI

tDS

tDH

R/W

tEZ

tDV

Figure 155. SPI 3-Wire Read Operation Timing

SCLK

SDIO

fSCLK

tLOW

tHI

tDS

tDH

R/W

tEZ

tDV

SDO

tEZ

Figure 156. SPI 4-Wire Read Operation Timing

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