AD9737ABBCZ datasheet(50/64 Pages) AD

50 / 64 page

AD9737A/AD9739A

Data Sheet

Rev. | Page 50 of 64

FINE

DELAY

DDR

DBx[13:1]

DATA RECEIVER CONTROLLER

DCI DELAY

SAMPLE

DELAY

DCI

PRE

POST

SAMPLE

DCI WINDOW PRE

DCI WINDOW POST

DCI WINDOW SAMPLE

DATA TO

CORE

DELAY

FINE

DELAY

FINE

DELAY

STATE MACHINE/

TRACKING LOOP

ELASTIC FIFO

DDR

180

FDAC

DIV-BY-4

270

DELAY

DDR

DCI

DELAY

PATH

SAMPLE

DELAY

PATH

DCO

Figure 160. Top Level Diagram of the Data Receiver Controller

The DIV-BY-4 circuit generates four clock phases that serve as

inputs to the data receiver controller. All DDR registers in the

data and DCI paths operate on both clock edges; however, for

clarity purposes, only the phases (that is, 0° and 90°) corresponding

to the positive edge of each path are shown. One of the DIV-BY-

4 phases is used to generate the DCO signal; therefore, the phase

relationship between DCO and clocks fed into the controller

remains fixed. Note that it is this attribute that allows possible

factory calibration of images and clock spurs that are attributed

to fDAC/4 modulation of the critical DAC clock.

After this data has been successively sampled into the first set of

registers, an elastic FIFO is used to transfer the data into the

AD9737A/AD9739A clock domain. To track any phase variation

continuously between the two clock domains, the data receiver

controller should always be enabled and placed into track mode

(Register 0x10, Bit 1 and Bit 0). Tracking mode operates cont-

inuously in the background to track delay variations between

the host and AD9737A/AD9739A clock domains. It does so by

ensuring that the DCI signal is sampled within a very narrow

window defined by two internally generated clocks (that is, PRE

and PST), as shown in Figure 161. Note that proper sampling of

the DCI signal can also be confirmed by monitoring the status

of DCI_PRE_PH0 (Register 0x0C, Bit 2) and DCI_PST_PH0

(Register 0x0C, Bit 0). If the delay settings are correct, the state

of DCI_ PRE_PH0 should be 0, and the state of DCI_PST_PH0

should be 1.

DCI

FINE DELAY

PST

FINE DELAY

PRE

FINE_DEL_SKEW

Figure 161. Pre- and Post-Delay Sampling Diagram

The skew or window width (FINE_DEL_SKEW) is set via

300 ps and resolution of 12 ps. It is recommended that the skew

be set to 36 ps (that is, Register 0x13 = 0x72) during initialization.

Note that the skew setting also affects the speed of the controller

loop, with tighter skew settings corresponding to longer

response time.

Data Receiver Controller Initialization Description

The data controller should be initialized and placed into track

mode as the second step in the SPI boot sequence. The following

steps are recommended for the initialization of the data receiver

controller:

1. Set FINE_DEL_SKEW to 2 for a larger DCI sampling window

(Register 0x13 = 0x72). Note that the default DCI_DEL and

SMP_DEL settings of 167 are optimum.

2. Disable the controller before enabling (that is, Register 0x10

= 0x00).

3. Enable the Rx controller in two steps: Register 0x10 = 0x02

followed by Register 0x10 = 0x03.

4. Wait 135 k clock cycles.

5. Read back Register 0x21 and confirm that it is equal to

0x05 to ensure that the DLL loop is locked and tracking.

6. Read back the DCI_DEL value to determine whether the

value falls within a user defined tracking guard band. If it

does not, go back to Step 2.

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