MPC5643L datasheet(20/136 Pages) FREESCALE

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MPC5643L Microcontroller Data Sheet, Rev. 8.1

Introduction

Freescale Semiconductor

The CRC unit has the following features:

•

3 sets of registers to allow 3 concurrent contexts with possibly different CRC computations, each with a selectable

polynomial and seed

•

Computes 16- or 32-bit wide CRC on the fly (single-cycle computation) and stores result in internal register.

The following standard CRC polynomials are implemented:

—x8 + x4 + x3 + x2 + 1 [8-bit CRC]

—x16 +x12 +x5 + 1 [16-bit CRC-CCITT]

— x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x +1

[32-bit CRC-ethernet(32)]

•

Key engine to be coupled with communication periphery where CRC application is added to allow implementation of

safe communication protocol

•

Offloads core from cycle-consuming CRC and helps checking configuration signature for safe start-up or periodic

procedures

•

CRC unit connected as peripheral bus on internal peripheral bus

•

DMA support

1.5.36

Redundancy Control and Checker Unit (RCCU)

The RCCU checks all outputs of the sphere of replication (addresses, data, control signals). It has the following features:

•

Duplicated module to guarantee highest possible diagnostic coverage (check of checker)

•

Multiple times replicated IPs are used as checkers on the SoR outputs

1.5.37

Junction temperature sensor

The junction temperature sensor provides a value via an ADC channel that can be used by software to calculate the device

junction temperature.

The key parameters of the junction temperature sensor include:

•

Nominal temperature range from –40 to 150 °C

•

Software temperature alarm via analog ADC comparator possible

1.5.38

Nexus Port Controller (NPC)

The NPC module provides real-time development support capabilities for this device in compliance with the IEEE-ISTO

5001-2003. This development support is supplied for MCUs without requiring external address and data pins for internal

visibility.

The NPC block interfaces to the host processor and internal buses to provide development support as per the IEEE-ISTO

5001-2003 Class 3+, including selected features from Class 4 standard.

The development support provided includes program trace, data trace, watchpoint trace, ownership trace, run-time access to the

MCUs internal memory map and access to the Power Architecture internal registers during halt. The Nexus interface also

supports a JTAG only mode using only the JTAG pins. The following features are implemented:

•

Full and reduced port modes

•

MCKO (message clock out) pin

•

4 or 12 MDO (message data out) pins1

•2 MSEO (message start/end out) pins

•EVTO (event out) pin

1. 4 MDO pins on 144 LQFP package, 12 MDO pins on 257 MAPBGA package.

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