SMM151/152

Summit Microelectronics, Inc

2131 3.0 1/20/2010

9

I

Diagram. Note 6.

Symbol

Description

Conditions

Min

Typ

Max

Units

SCL Clock Frequency

0

100

KHz

Clock Low Period

4.7

μs

Clock High Period

4.0

μs

Bus Free Time

Before New Transmission, Note 5

4.7

μs

Start Condition Setup Time

4.7

μs

Start Condition Hold Time

4.0

μs

Stop Condition Setup Time

4.7

μs

Clock Edge to Data Valid

SCL low to valid SDA (cycle n)

0.2

3.5

μs

Data Output Hold Time

SCL low (cycle n+1) to SDA

change

0.2

μs

SCL and SDA Rise Time

Note 5

1000

ns

SCL and SDA Fall Time

Note 5

300

ns

Data In Setup Time

250

ns

Data In Hold Time

0

ns

TI

Noise Filter SCL and SDA

Noise suppression

100

ns

Write Cycle Time

5

ms

Note 5: Not 100% Production tested. Guaranteed by Design and/or Characterization.

Note 6: All electrical parameters are guaranteed to function over the stated VDD, VCS and temperature range. Electrical parameters not specified as

"guaranteed by design" are tested with a VDD voltage required of the specific application. For example, if the device is to be operated at 3.3V and VCS

supply of 12V, it is tested with a VDD supply of 3.3V, +-10% and a VCS supply of 12V, +-10%.

TIMING DIAGRAMS

t

R

t

F

t

HIGH

t

LOW

t

SU:STA

t

HD:STA

t

SU:DAT

t

HD:DAT

t

SU:STO

t

BUF

t

DH

t

AA

SCL

SDA

(IN)

SDA

(OUT)

t

WR (For Write Operation Only)

Figure 3. Basic I