SMM151_10 datasheet(4/24 Pages) SUMMIT

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SMM151/152

Summit Microelectronics, Inc

2131 3.0 1/20/2010

Number

Type

Pin Name

Pin Description

I/O

SDA

2C Bi-directional data line

SCL

2C clock input.

The address pins are biased either to VDD, GND or left floating. This allows

for a total of 21 distinct device addresses. When communicating with the

SMM151/2 over the 2-wire bus these pins provide a mechanism for

assigning a unique bus address.

I/O

GPIO0,1,2,3

SMM152: General purpose inputs/outputs.

3, 9, 22, 27

SMM151: No Connect.

Programmable Write Protect active high/low input. When asserted, writes to

the configuration registers and general purpose EE are not allowed. The

WP input is internally tied to VDD with a 50K

Ω resistor.

10, 13

CAP

CAPM+, -

External capacitor inputs used to filter the VM+/VM- inputs, 0.22

μF.

TRIM

Output voltage used to control and/or margin converter voltages. Connect to

the converter trim input.

VM+

Voltage monitor input. Connect to the DC-DC converter positive sense line

or its +Vout pin.

VM-

Voltage monitor input. Connect to the DC-DC converter negative sense line

or its -Vout pin.

CS+

Current monitor input + side. Kelvin connect to the input supply side of the

current sense resistor.

CS-

Current monitor input - side. Kelvin connect to the load side of the current

sense resistor.

PWR

VREF

Internal reference voltage of 1.25V. Connect to GND through a 0.1uF

capacitor to improve noise immunity.

CAPC

External capacitor input used to filter the CS+/CS- input. Typical value: 1uF.

PWR

VDD

Power supply of the part.

PWR

VDD_CAP

External capacitor input used to filter the internal VDD supply rail.

GND

Ground of the part. The SMM151/2 ground pin should be connected to the

ground of the device under control or to a star point ground. PCB layout

should take into consideration ground drops.

MUP

Margin up command input. Asserted high. The MUP input is internally tied to

VDD with a 50K

Ω resistor.

MDN

Margin down command input. Asserted high. The MDN input is internally

tied to VDD with a 50K

Ω resistor.

COMP1

COMP2

COMP1 and COMP2 are high impedance inputs, each connected internally

to a comparator and compared against the internally programmable VREF

voltage. Each comparator can be independently programmed to monitor for

UV or OV. The monitor level is set externally with a resistive voltage

divider.

FAULT#

When either of the COMP1 or COMP2 inputs are in fault the open-drain

FAULT# output will be pulled low. A configuration option exists to disable

the FAULT# output while the device is margining.

PIN DESCRIPTIONS

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