RT8288A datasheet(11/14 Pages) RICHTEK

11 / 14 page

RT8288A

DS8288A-03

June 2012

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

This formula has a maximum at VIN = 2VOUT, where IRMS =

IOUT / 2. This simple worst case condition is commonly

used for design because even significant deviations do

not offer much relief.

Table 3. Suggested Capacitors for CIN and COUT

Location

Component Supplier

Part No.

Capacitance (

μF)

Case Size

CIN

MURATA

GRM32ER71C226M

1210

CIN

TDK

C3225X5R1C226M

1210

COUT

MURATA

GRM31CR60J476M

1206

COUT

TDK

C3225X5R0J476M

1210

COUT

MURATA

GRM32ER71C226M

1210

COUT

TDK

C3225X5R1C226M

1210

The selection of COUT is determined by the required ESR

to minimize voltage ripple.

Moreover, the amount of bulk capacitance is also a key

for COUT selection to ensure that the control loop is stable.

Loop stability can be checked by viewing the load transient

response.

The output ripple,

ΔVOUT, is determined by :

OUT

ESR

8fC

⎡⎤

Δ≤ Δ

⎢⎥

⎣⎦

Higher values, lower cost ceramic capacitors are now

becoming available in smaller case sizes. Their high ripple

current, high voltage rating and low ESR make them ideal

for switching regulator applications. However, care must

be taken when these capacitors are used at input and

output. When a ceramic capacitor is used at the input

and the power is supplied by a wall adapter through long

wires, a load step at the output can induce ringing at the

input, VIN. At best, this ringing can couple to the output

and be mistaken as loop instability. At worst, a sudden

inrush of current through the long wires can potentially

cause a voltage spike at VIN large enough to damage the

part.

Thermal Shutdown

Thermal shutdown is implemented to prevent the chip from

operating at excessively high temperatures. When the

junction temperature is higher than 150

°C, the chip will

shut down the switching operation. The chip will

automatically resume switching, once the junction

temperature cools down by approximately 30

°C.

EMI Consideration

Since parasitic inductance and capacitance effects in PCB

circuitry would cause a spike voltage on SW pin when

high side MOSFET is turned-on/off, this spike voltage on

SW may impact on EMI performance in the system. In

order to enhance EMI performance, there are two methods

to suppress the spike voltage. One way is by placing an

R-C snubber (RS*, CS*) between SW and GND and locating

them as close as possible to the SW pin, as shown in

Figure 5. Another method is by adding a resistor in series

with the bootstrap capacitor, CBOOT, but this method will

decrease the driving capability to the high side MOSFET.

It is strongly recommended to reserve the R-C snubber

during PCB layout for EMI improvement. Moreover,

reducing the SW trace area and keeping the main power

in a small loop will be helpful on EMI performance. For

detailed PCB layout guide, please refer to the section

Layout Considerations.

Choose a capacitor rated at a higher temperature than

required. Several capacitors may also be paralleled to

meet size or height requirements in the design.

For the input capacitor, one 22

μF low ESR ceramic

capacitors are recommended. For the recommended

capacitor, please refer to Table 3 for more detail.

RT8288A Arkusz danych(PDF) 11 Page - Richtek Technology Corporation

RT8288A Arkusz danych(HTML) 11 Page - Richtek Technology Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Arkusz danych Pobierz

Link URL